Search

Jack Cooper

Examiner (ID: 2250)

Most Active Art Unit
1103
Art Unit(s)
1108, 1111, 1107, 1103, 1109
Total Applications
844
Issued Applications
585
Pending Applications
2
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7167158 [patent_doc_number] => 20050086545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Information handling system including fast acting current monitoring and throttling capability' [patent_app_type] => utility [patent_app_number] => 10/688546 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3821 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086545.pdf [firstpage_image] =>[orig_patent_app_number] => 10688546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688546
Information handling system including fast acting current monitoring and throttling capability Oct 16, 2003 Abandoned
Array ( [id] => 765456 [patent_doc_number] => 07017069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'PWM control circuit, microcomputer and electronic equipment' [patent_app_type] => utility [patent_app_number] => 10/681302 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6700 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017069.pdf [firstpage_image] =>[orig_patent_app_number] => 10681302 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681302
PWM control circuit, microcomputer and electronic equipment Oct 8, 2003 Issued
Array ( [id] => 562537 [patent_doc_number] => 07165171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Wireless human interface device host interface supporting both BIOS and OS interface operations' [patent_app_type] => utility [patent_app_number] => 10/675803 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8131 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165171.pdf [firstpage_image] =>[orig_patent_app_number] => 10675803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675803
Wireless human interface device host interface supporting both BIOS and OS interface operations Sep 29, 2003 Issued
Array ( [id] => 527171 [patent_doc_number] => 07200762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Providing a low-power state processor voltage in accordance with a detected processor type' [patent_app_type] => utility [patent_app_number] => 10/675793 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1814 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200762.pdf [firstpage_image] =>[orig_patent_app_number] => 10675793 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675793
Providing a low-power state processor voltage in accordance with a detected processor type Sep 29, 2003 Issued
Array ( [id] => 261884 [patent_doc_number] => 07574618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Interface circuit' [patent_app_type] => utility [patent_app_number] => 10/663977 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6874 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574618.pdf [firstpage_image] =>[orig_patent_app_number] => 10663977 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663977
Interface circuit Sep 16, 2003 Issued
Array ( [id] => 7456325 [patent_doc_number] => 20040052347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Gateway card, gateway device, gateway control method, and computer product' [patent_app_type] => new [patent_app_number] => 10/658341 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4829 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20040052347.pdf [firstpage_image] =>[orig_patent_app_number] => 10658341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658341
Gateway card, gateway device, gateway control method, and computer product Sep 9, 2003 Abandoned
Array ( [id] => 481540 [patent_doc_number] => 07228449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method and device for transmitting a selection signal from a processor to a peripheral by violating a symmetry of transmission of a data signal' [patent_app_type] => utility [patent_app_number] => 10/643616 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1972 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228449.pdf [firstpage_image] =>[orig_patent_app_number] => 10643616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/643616
Method and device for transmitting a selection signal from a processor to a peripheral by violating a symmetry of transmission of a data signal Aug 17, 2003 Issued
Array ( [id] => 5794993 [patent_doc_number] => 20060015674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Self-booting software defined radio module' [patent_app_type] => utility [patent_app_number] => 10/618950 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015674.pdf [firstpage_image] =>[orig_patent_app_number] => 10618950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618950
Self-booting software defined radio module Jul 13, 2003 Issued
Array ( [id] => 7472786 [patent_doc_number] => 20040199802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Method of synchronizing dual clock frequencies' [patent_app_type] => new [patent_app_number] => 10/455372 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2578 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20040199802.pdf [firstpage_image] =>[orig_patent_app_number] => 10455372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455372
Method and circuit for synchronizing a higher frequency clock and a lower frequency clock Jun 5, 2003 Issued
Array ( [id] => 653631 [patent_doc_number] => 07114069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor' [patent_app_type] => utility [patent_app_number] => 10/420221 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3375 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/114/07114069.pdf [firstpage_image] =>[orig_patent_app_number] => 10420221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420221
Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor Apr 21, 2003 Issued
Array ( [id] => 549379 [patent_doc_number] => 07185217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-27 [patent_title] => 'Method and apparatus for providing a clock signal to a plurality of destination receivers in an integrated circuit environment' [patent_app_type] => utility [patent_app_number] => 10/412985 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2744 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185217.pdf [firstpage_image] =>[orig_patent_app_number] => 10412985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412985
Method and apparatus for providing a clock signal to a plurality of destination receivers in an integrated circuit environment Apr 13, 2003 Issued
Array ( [id] => 7477003 [patent_doc_number] => 20040098577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Dynamically booting processor code memory with wait instruction' [patent_app_type] => new [patent_app_number] => 10/411632 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3071 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098577.pdf [firstpage_image] =>[orig_patent_app_number] => 10411632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411632
Integrated circuit with DMA module for loading portions of code to a code memory for execution by a host processor that controls a video decoder Apr 10, 2003 Issued
Array ( [id] => 7196363 [patent_doc_number] => 20040205328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Method and apparatus for loading microcode' [patent_app_type] => new [patent_app_number] => 10/411414 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3983 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205328.pdf [firstpage_image] =>[orig_patent_app_number] => 10411414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411414
Method and apparatus for updating a microcode image in a memory Apr 9, 2003 Issued
Array ( [id] => 7196579 [patent_doc_number] => 20040205368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Virtual real time clock maintenance in a logically partitioned computer system' [patent_app_type] => new [patent_app_number] => 10/411455 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5134 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205368.pdf [firstpage_image] =>[orig_patent_app_number] => 10411455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411455
Virtual real time clock maintenance in a logically partitioned computer system Apr 9, 2003 Issued
Array ( [id] => 7196576 [patent_doc_number] => 20040205367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Integrated circuit with oscillating signal detector' [patent_app_type] => new [patent_app_number] => 10/411427 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205367.pdf [firstpage_image] =>[orig_patent_app_number] => 10411427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411427
Integrated circuit and method for detecting the state of an oscillating signal Apr 9, 2003 Issued
Array ( [id] => 7196360 [patent_doc_number] => 20040205327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'System and method for computer hardware identification' [patent_app_type] => new [patent_app_number] => 10/411164 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4386 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205327.pdf [firstpage_image] =>[orig_patent_app_number] => 10411164 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411164
System and method for computer hardware identification Apr 8, 2003 Issued
Array ( [id] => 637583 [patent_doc_number] => 07131022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Timing generator system for outputting clock signals to components of an imaging system according to decoded timing control instructions' [patent_app_type] => utility [patent_app_number] => 10/410990 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7308 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/131/07131022.pdf [firstpage_image] =>[orig_patent_app_number] => 10410990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410990
Timing generator system for outputting clock signals to components of an imaging system according to decoded timing control instructions Apr 8, 2003 Issued
Array ( [id] => 568981 [patent_doc_number] => 07171576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency' [patent_app_type] => utility [patent_app_number] => 10/410385 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4064 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/171/07171576.pdf [firstpage_image] =>[orig_patent_app_number] => 10410385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410385
Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency Apr 8, 2003 Issued
Array ( [id] => 7196589 [patent_doc_number] => 20040205371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Configuration for adjusting CPU speed and method thereof' [patent_app_type] => new [patent_app_number] => 10/409180 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1226 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205371.pdf [firstpage_image] =>[orig_patent_app_number] => 10409180 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/409180
Configuration for adjusting CPU speed and method thereof Apr 8, 2003 Abandoned
Array ( [id] => 96961 [patent_doc_number] => 07734943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Low power display refresh' [patent_app_type] => utility [patent_app_number] => 10/407758 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1904 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734943.pdf [firstpage_image] =>[orig_patent_app_number] => 10407758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407758
Low power display refresh Apr 2, 2003 Issued
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