Search

Jack Cooper

Examiner (ID: 2250)

Most Active Art Unit
1103
Art Unit(s)
1108, 1111, 1107, 1103, 1109
Total Applications
844
Issued Applications
585
Pending Applications
2
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 716982 [patent_doc_number] => 07058835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'System, method and apparatus for controlling supply of backup power to first and second power planes in the event of a power failure of a main power supply' [patent_app_type] => utility [patent_app_number] => 10/103012 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7406 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/058/07058835.pdf [firstpage_image] =>[orig_patent_app_number] => 10103012 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103012
System, method and apparatus for controlling supply of backup power to first and second power planes in the event of a power failure of a main power supply Mar 20, 2002 Issued
Array ( [id] => 248857 [patent_doc_number] => 07587618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Computer system and unit, and power supply control method therefor' [patent_app_type] => utility [patent_app_number] => 10/102352 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6684 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587618.pdf [firstpage_image] =>[orig_patent_app_number] => 10102352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102352
Computer system and unit, and power supply control method therefor Mar 19, 2002 Issued
Array ( [id] => 5791612 [patent_doc_number] => 20020162035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Interface circuit and disk drive apparatus' [patent_app_type] => new [patent_app_number] => 10/082829 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1844 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20020162035.pdf [firstpage_image] =>[orig_patent_app_number] => 10082829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082829
Interface circuit and disk drive apparatus Feb 19, 2002 Abandoned
Array ( [id] => 6698209 [patent_doc_number] => 20030110403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'System for shared power supply in computer peripheral devices' [patent_app_type] => new [patent_app_number] => 10/016254 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5142 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110403.pdf [firstpage_image] =>[orig_patent_app_number] => 10016254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016254
System for shared power supply in computer peripheral devices Dec 9, 2001 Abandoned
Array ( [id] => 6451563 [patent_doc_number] => 20020129234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Microprocessor comprising input means in the test mode' [patent_app_type] => new [patent_app_number] => 09/995251 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3625 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129234.pdf [firstpage_image] =>[orig_patent_app_number] => 09995251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995251
Method and apparatus for preventing a microprocessor from erroneously entering into a test mode during initialization Nov 26, 2001 Issued
Array ( [id] => 6211662 [patent_doc_number] => 20020073352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Data processor and data processing system' [patent_app_type] => new [patent_app_number] => 09/993704 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8219 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073352.pdf [firstpage_image] =>[orig_patent_app_number] => 09993704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/993704
Data processor and data processing system Nov 26, 2001 Issued
Array ( [id] => 6766962 [patent_doc_number] => 20030101362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method and apparatus for enabling a self suspend mode for a processor' [patent_app_type] => new [patent_app_number] => 09/995171 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3301 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101362.pdf [firstpage_image] =>[orig_patent_app_number] => 09995171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995171
Method and apparatus for enabling a self suspend mode for a processor Nov 25, 2001 Issued
Array ( [id] => 6085736 [patent_doc_number] => 20020083356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method and apparatus to enhance processor power management' [patent_app_type] => new [patent_app_number] => 09/994982 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083356.pdf [firstpage_image] =>[orig_patent_app_number] => 09994982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994982
Method and apparatus to enhance processor power management Nov 25, 2001 Issued
Array ( [id] => 649088 [patent_doc_number] => 07120806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-10 [patent_title] => 'Method for setting a power operating mode transition interval of a disk drive in a mobile device based on application category' [patent_app_type] => utility [patent_app_number] => 10/105493 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2703 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120806.pdf [firstpage_image] =>[orig_patent_app_number] => 10105493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/105493
Method for setting a power operating mode transition interval of a disk drive in a mobile device based on application category Oct 30, 2001 Issued
Array ( [id] => 1085070 [patent_doc_number] => 06834353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Method and apparatus for reducing power consumption of a processing integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/682816 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5679 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834353.pdf [firstpage_image] =>[orig_patent_app_number] => 09682816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/682816
Method and apparatus for reducing power consumption of a processing integrated circuit Oct 21, 2001 Issued
Array ( [id] => 6245475 [patent_doc_number] => 20020046356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Integrated circuit with multiprocessor architecture' [patent_app_type] => new [patent_app_number] => 09/973888 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3552 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046356.pdf [firstpage_image] =>[orig_patent_app_number] => 09973888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973888
Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture Oct 10, 2001 Issued
Array ( [id] => 6814999 [patent_doc_number] => 20030074549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method and system for implementing a diagnostic or correciton boot image over a network connection' [patent_app_type] => new [patent_app_number] => 09/975248 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2638 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074549.pdf [firstpage_image] =>[orig_patent_app_number] => 09975248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975248
System for implementing a diagnostic or correction boot image over a network connection Oct 10, 2001 Issued
Array ( [id] => 984663 [patent_doc_number] => 06928540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method and system for synchronizing a clock frequency multiplier with a CPU using a serial initialization packet protocol' [patent_app_type] => utility [patent_app_number] => 09/974559 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3558 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928540.pdf [firstpage_image] =>[orig_patent_app_number] => 09974559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974559
Method and system for synchronizing a clock frequency multiplier with a CPU using a serial initialization packet protocol Oct 8, 2001 Issued
Array ( [id] => 6817066 [patent_doc_number] => 20030068024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Communication system activation' [patent_app_type] => new [patent_app_number] => 09/972717 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11887 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068024.pdf [firstpage_image] =>[orig_patent_app_number] => 09972717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972717
Communication system activation Oct 4, 2001 Abandoned
Array ( [id] => 6722438 [patent_doc_number] => 20030056128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Apparatus and method for a selectable Ron driver impedance' [patent_app_type] => new [patent_app_number] => 09/957104 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5483 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056128.pdf [firstpage_image] =>[orig_patent_app_number] => 09957104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957104
Apparatus and method for a selectable Ron driver impedance Sep 19, 2001 Abandoned
Array ( [id] => 943645 [patent_doc_number] => 06971035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Method and system for reducing power consumption of a multi-function electronic apparatus that is adapted to receive power from a host system' [patent_app_type] => utility [patent_app_number] => 09/938121 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4413 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/971/06971035.pdf [firstpage_image] =>[orig_patent_app_number] => 09938121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938121
Method and system for reducing power consumption of a multi-function electronic apparatus that is adapted to receive power from a host system Aug 22, 2001 Issued
Array ( [id] => 984719 [patent_doc_number] => 06928574 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain' [patent_app_type] => utility [patent_app_number] => 09/938210 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4540 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928574.pdf [firstpage_image] =>[orig_patent_app_number] => 09938210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938210
System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain Aug 22, 2001 Issued
Array ( [id] => 981739 [patent_doc_number] => 06931562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'System and method for transferring data from a higher frequency clock domain to a lower frequency clock domain' [patent_app_type] => utility [patent_app_number] => 09/938206 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4860 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931562.pdf [firstpage_image] =>[orig_patent_app_number] => 09938206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938206
System and method for transferring data from a higher frequency clock domain to a lower frequency clock domain Aug 22, 2001 Issued
Array ( [id] => 787672 [patent_doc_number] => 06990593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for diverting power reserves and shifting activities according to activity priorities in a server cluster in the event of a power interruption' [patent_app_type] => utility [patent_app_number] => 09/919134 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990593.pdf [firstpage_image] =>[orig_patent_app_number] => 09919134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919134
Method for diverting power reserves and shifting activities according to activity priorities in a server cluster in the event of a power interruption Jul 30, 2001 Issued
Array ( [id] => 6746659 [patent_doc_number] => 20030023842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Remote processor reset apparatus and method' [patent_app_type] => new [patent_app_number] => 09/915923 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1314 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023842.pdf [firstpage_image] =>[orig_patent_app_number] => 09915923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915923
Remote processor reset apparatus and method Jul 25, 2001 Abandoned
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