Search

Jack Cooper

Examiner (ID: 2250)

Most Active Art Unit
1103
Art Unit(s)
1108, 1111, 1107, 1103, 1109
Total Applications
844
Issued Applications
585
Pending Applications
2
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1085072 [patent_doc_number] => 06834354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-21 [patent_title] => 'Method and apparatus for assigning tasks in an information processing system to optimize power consumption versus performance of the system' [patent_app_type] => B1 [patent_app_number] => 09/762873 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8498 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834354.pdf [firstpage_image] =>[orig_patent_app_number] => 09762873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/762873
Method and apparatus for assigning tasks in an information processing system to optimize power consumption versus performance of the system Feb 13, 2001 Issued
Array ( [id] => 1129680 [patent_doc_number] => 06795914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'System and method for selectively executing programs in response to a reboot in a computer system' [patent_app_type] => B2 [patent_app_number] => 09/769853 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2981 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795914.pdf [firstpage_image] =>[orig_patent_app_number] => 09769853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769853
System and method for selectively executing programs in response to a reboot in a computer system Jan 24, 2001 Issued
Array ( [id] => 716979 [patent_doc_number] => 07058833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'System and method for minimized power consumption for frame and cell data transmission systems' [patent_app_type] => utility [patent_app_number] => 09/765223 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7608 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/058/07058833.pdf [firstpage_image] =>[orig_patent_app_number] => 09765223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765223
System and method for minimized power consumption for frame and cell data transmission systems Jan 17, 2001 Issued
Array ( [id] => 5971593 [patent_doc_number] => 20020091955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Wake-up circuit for an electronic system and method therefor' [patent_app_type] => new [patent_app_number] => 09/755322 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6781 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091955.pdf [firstpage_image] =>[orig_patent_app_number] => 09755322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755322
Method and apparatus for determining whether to wake up a system by detecting a status of a push button switch that is remotely located from the system Jan 4, 2001 Issued
Array ( [id] => 5971498 [patent_doc_number] => 20020091917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Method for control of multiple operating systems and electronic machines applicable thereto' [patent_app_type] => new [patent_app_number] => 09/754978 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1298 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091917.pdf [firstpage_image] =>[orig_patent_app_number] => 09754978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754978
Method for control of multiple operating systems and electronic machines applicable thereto Jan 4, 2001 Abandoned
Array ( [id] => 5861383 [patent_doc_number] => 20020124196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Computer system having low energy consumption' [patent_app_type] => new [patent_app_number] => 09/755861 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6033 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124196.pdf [firstpage_image] =>[orig_patent_app_number] => 09755861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755861
Computer system having low energy consumption Jan 4, 2001 Issued
Array ( [id] => 5971503 [patent_doc_number] => 20020091919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Method, system, and program for selecting one of multiple code images to execute following a reboot operation' [patent_app_type] => new [patent_app_number] => 09/755814 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4939 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091919.pdf [firstpage_image] =>[orig_patent_app_number] => 09755814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755814
System and method using a first counter and a second counter to select a code image during a reboot routine Jan 4, 2001 Issued
Array ( [id] => 6649146 [patent_doc_number] => 20020087903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Mechanism for managing power generated in a computer system' [patent_app_type] => new [patent_app_number] => 09/752575 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1693 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087903.pdf [firstpage_image] =>[orig_patent_app_number] => 09752575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752575
Mechanism for managing power generated in a computer system Dec 28, 2000 Abandoned
Array ( [id] => 7621115 [patent_doc_number] => 06978386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Method and apparatus for regulating current for programmable logic controllers' [patent_app_type] => utility [patent_app_number] => 09/751233 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2396 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978386.pdf [firstpage_image] =>[orig_patent_app_number] => 09751233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751233
Method and apparatus for regulating current for programmable logic controllers Dec 27, 2000 Issued
Array ( [id] => 6085923 [patent_doc_number] => 20020083427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Embedded system capable of rapidly updating software and method for rapidly updating software of embedded system' [patent_app_type] => new [patent_app_number] => 09/745932 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1577 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083427.pdf [firstpage_image] =>[orig_patent_app_number] => 09745932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745932
Embedded system capable of rapidly updating software and method for rapidly updating software of embedded system Dec 25, 2000 Abandoned
Array ( [id] => 1170330 [patent_doc_number] => 06766459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Time keeping apparatus and method for controlling the same' [patent_app_type] => B2 [patent_app_number] => 09/745968 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14655 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766459.pdf [firstpage_image] =>[orig_patent_app_number] => 09745968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745968
Time keeping apparatus and method for controlling the same Dec 20, 2000 Issued
Array ( [id] => 684826 [patent_doc_number] => 07085939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and apparatus for supplying power to a bus-controlled component of a computer' [patent_app_type] => utility [patent_app_number] => 09/737455 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4363 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085939.pdf [firstpage_image] =>[orig_patent_app_number] => 09737455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737455
Method and apparatus for supplying power to a bus-controlled component of a computer Dec 13, 2000 Issued
Array ( [id] => 7622325 [patent_doc_number] => 06687841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Wide frequency range PLL clock generating circuit with delta sigma modulating circuitry for reducing the time changing ratio of the input voltage of a voltage controlled oscillator' [patent_app_type] => B1 [patent_app_number] => 09/673820 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6341 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687841.pdf [firstpage_image] =>[orig_patent_app_number] => 09673820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/673820
Wide frequency range PLL clock generating circuit with delta sigma modulating circuitry for reducing the time changing ratio of the input voltage of a voltage controlled oscillator Dec 11, 2000 Issued
Array ( [id] => 1170084 [patent_doc_number] => 06763471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Single chip microcomputer with reduced channel leakage current during a stable low speed operation state' [patent_app_type] => B1 [patent_app_number] => 09/723386 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7859 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763471.pdf [firstpage_image] =>[orig_patent_app_number] => 09723386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723386
Single chip microcomputer with reduced channel leakage current during a stable low speed operation state Nov 27, 2000 Issued
Array ( [id] => 431433 [patent_doc_number] => 07269746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Method of transmitting identification data from an option pack to a main unit before the option pack is fully powered' [patent_app_type] => utility [patent_app_number] => 09/722889 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10096 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269746.pdf [firstpage_image] =>[orig_patent_app_number] => 09722889 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722889
Method of transmitting identification data from an option pack to a main unit before the option pack is fully powered Nov 26, 2000 Issued
Array ( [id] => 1186715 [patent_doc_number] => 06738922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal' [patent_app_type] => B1 [patent_app_number] => 09/680679 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4762 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738922.pdf [firstpage_image] =>[orig_patent_app_number] => 09680679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680679
Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal Oct 5, 2000 Issued
Array ( [id] => 1214548 [patent_doc_number] => 06715095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method and circuitry for switching from a synchronous mode of operation to an asynchronous mode of operation without any loss of data' [patent_app_type] => B1 [patent_app_number] => 09/677390 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2418 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715095.pdf [firstpage_image] =>[orig_patent_app_number] => 09677390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677390
Method and circuitry for switching from a synchronous mode of operation to an asynchronous mode of operation without any loss of data Oct 1, 2000 Issued
Array ( [id] => 971477 [patent_doc_number] => 06941480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-06 [patent_title] => 'Method and apparatus for transitioning a processor state from a first performance mode to a second performance mode' [patent_app_type] => utility [patent_app_number] => 09/677263 [patent_app_country] => US [patent_app_date] => 2000-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3615 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/941/06941480.pdf [firstpage_image] =>[orig_patent_app_number] => 09677263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677263
Method and apparatus for transitioning a processor state from a first performance mode to a second performance mode Sep 29, 2000 Issued
Array ( [id] => 1097461 [patent_doc_number] => 06826702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load' [patent_app_type] => B1 [patent_app_number] => 09/671690 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5334 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826702.pdf [firstpage_image] =>[orig_patent_app_number] => 09671690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671690
Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load Sep 27, 2000 Issued
Array ( [id] => 7622322 [patent_doc_number] => 06687844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal' [patent_app_type] => B1 [patent_app_number] => 09/671314 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3379 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687844.pdf [firstpage_image] =>[orig_patent_app_number] => 09671314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671314
Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal Sep 27, 2000 Issued
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