Jack Cooper

Array ( [id] => 1097455 [patent_doc_number] => 06826701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Re-running general purpose event control methods in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/553071 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10840 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826701.pdf [firstpage_image] =>[orig_patent_app_number] => 09553071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1177786 [patent_doc_number] => 06760847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method for performing subscriber loop disturber recognition by comparing measured sample power spectral densities with a set of known power spectral densities' [patent_app_type] => B1 [patent_app_number] => 09/548746 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4643 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760847.pdf [firstpage_image] =>[orig_patent_app_number] => 09548746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1240914 [patent_doc_number] => 06691238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'System for disabling remote wake events on a remote wake line that is coupled to a front panel switch wake line' [patent_app_type] => B1 [patent_app_number] => 09/539519 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3616 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691238.pdf [firstpage_image] =>[orig_patent_app_number] => 09539519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1066819 [patent_doc_number] => 06851069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method, apparatus, and system for high speed data transfer using programmable DLL without using strobes for reads and writes' [patent_app_type] => utility [patent_app_number] => 09/539082 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2055 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851069.pdf [firstpage_image] =>[orig_patent_app_number] => 09539082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1284788 [patent_doc_number] => 06651181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Clocking scheme for programmable logic device' [patent_app_type] => B1 [patent_app_number] => 09/537376 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3893 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651181.pdf [firstpage_image] =>[orig_patent_app_number] => 09537376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1279679 [patent_doc_number] => 06654880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method and apparatus for reducing system down time by restarting system using a primary memory before dumping contents of a standby memory to external storage' [patent_app_type] => B1 [patent_app_number] => 09/526635 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4760 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654880.pdf [firstpage_image] =>[orig_patent_app_number] => 09526635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7633037 [patent_doc_number] => 06658583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'PWM control circuit, microcomputer and electronic equipment' [patent_app_type] => B1 [patent_app_number] => 09/525261 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658583.pdf [firstpage_image] =>[orig_patent_app_number] => 09525261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1366898 [patent_doc_number] => 06584578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Arbitration method and circuit for control of integrated circuit double data rate (DDR) memory device output first-in, first-out (FIFO) registers' [patent_app_type] => B1 [patent_app_number] => 09/524644 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4083 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584578.pdf [firstpage_image] =>[orig_patent_app_number] => 09524644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1284766 [patent_doc_number] => 06651177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Circuit and method of providing power to an external peripheral' [patent_app_type] => B1 [patent_app_number] => 09/502201 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2080 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651177.pdf [firstpage_image] =>[orig_patent_app_number] => 09502201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429525 [patent_doc_number] => 06530030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Apparatus for and a method of clock tree synthesis allocation wiring' [patent_app_type] => B1 [patent_app_number] => 09/500632 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3574 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530030.pdf [firstpage_image] =>[orig_patent_app_number] => 09500632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1234440 [patent_doc_number] => 06697956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method and apparatus for phrase synchronizing a plurality of microcontrollers of a distributed microcontroller network in a brake-by-wire automobile braking system' [patent_app_type] => B1 [patent_app_number] => 09/495197 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1872 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697956.pdf [firstpage_image] =>[orig_patent_app_number] => 09495197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1366639 [patent_doc_number] => 06584559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Firmware download scheme for high-availability systems' [patent_app_type] => B1 [patent_app_number] => 09/493633 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2685 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584559.pdf [firstpage_image] =>[orig_patent_app_number] => 09493633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1192524 [patent_doc_number] => 06735691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'System and method for the automated migration of configuration information' [patent_app_type] => B1 [patent_app_number] => 09/492899 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6258 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735691.pdf [firstpage_image] =>[orig_patent_app_number] => 09492899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7631536 [patent_doc_number] => 06665801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method and apparatus for charging a self powered USB device at different charge rates according to the charge level of a rechargeable element on the device' [patent_app_type] => B1 [patent_app_number] => 09/492468 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5994 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665801.pdf [firstpage_image] =>[orig_patent_app_number] => 09492468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311592 [patent_doc_number] => 06625740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Dynamically activating and deactivating selected circuit blocks of a data processing integrated circuit during execution of instructions according to power code bits appended to selected instructions' [patent_app_type] => B1 [patent_app_number] => 09/482822 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3484 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625740.pdf [firstpage_image] =>[orig_patent_app_number] => 09482822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1236391 [patent_doc_number] => 06694440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Computer, network controller, and system and remote activating method using the computer and controller' [patent_app_type] => B1 [patent_app_number] => 09/482016 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4959 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694440.pdf [firstpage_image] =>[orig_patent_app_number] => 09482016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429266 [patent_doc_number] => 06513126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'SYSTEM FOR MODELING A PROCESSOR-ENCODER INTERFACE BY COUNTING NUMBER OF FAST CLOCK CYCLES OCCURING IN ONE SLOWER CLOCK CYCLE AND TRIGGERING A DOMAIN MODULE IF FAST CLOCK REACHES THE CORRESPONDING NUMBER OF CYCLES' [patent_app_type] => B1 [patent_app_number] => 09/477692 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513126.pdf [firstpage_image] =>[orig_patent_app_number] => 09477692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361603 [patent_doc_number] => 06587942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Circuit for converting input serial data in a plurality of possible formats into output data in parallel format by interpreting input data format indication information' [patent_app_type] => B1 [patent_app_number] => 09/476580 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587942.pdf [firstpage_image] =>[orig_patent_app_number] => 09476580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1337402 [patent_doc_number] => 06604202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Low power processor' [patent_app_type] => B1 [patent_app_number] => 09/442148 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3785 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604202.pdf [firstpage_image] =>[orig_patent_app_number] => 09442148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1240904 [patent_doc_number] => 06691233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Battery operated ink capture device that operates in a normal power mode during active use and a minimum power mode during absence of active use' [patent_app_type] => B1 [patent_app_number] => 09/442603 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6534 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691233.pdf [firstpage_image] =>[orig_patent_app_number] => 09442603 [rel_patent_id] =>[rel_patent_doc_number] =>)