Search

Jack I Berman

Examiner (ID: 1875, Phone: (571)272-2468 , Office: P/2881 )

Most Active Art Unit
2506
Art Unit(s)
2899, 2878, 2506, 2881
Total Applications
2582
Issued Applications
2249
Pending Applications
67
Abandoned Applications
266

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4762679 [patent_doc_number] => 20080173888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Light-emitting diode chip package body and packaging method thereof' [patent_app_type] => utility [patent_app_number] => 12/007276 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5983 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20080173888.pdf [firstpage_image] =>[orig_patent_app_number] => 12007276 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/007276
Light-emitting diode chip package body and packaging method thereof Jan 8, 2008 Issued
Array ( [id] => 5578721 [patent_doc_number] => 20090174067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING' [patent_app_type] => utility [patent_app_number] => 11/971470 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174067.pdf [firstpage_image] =>[orig_patent_app_number] => 11971470 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971470
Airgap-containing interconnect structure with patternable low-k material and method of fabricating Jan 8, 2008 Issued
Array ( [id] => 4925140 [patent_doc_number] => 20080164503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Ferroelectric Memory Devices Having a Protruding Bottom Electrode and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 11/970770 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20080164503.pdf [firstpage_image] =>[orig_patent_app_number] => 11970770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970770
Ferroelectric Memory Devices Having a Protruding Bottom Electrode and Methods of Forming the Same Jan 7, 2008 Abandoned
Array ( [id] => 5578738 [patent_doc_number] => 20090174084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT (FLI) IN MICROELECTRONICS PACKAGING' [patent_app_type] => utility [patent_app_number] => 11/970130 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2467 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174084.pdf [firstpage_image] =>[orig_patent_app_number] => 11970130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970130
Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging Jan 6, 2008 Issued
Array ( [id] => 4952688 [patent_doc_number] => 20080185712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/968840 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185712.pdf [firstpage_image] =>[orig_patent_app_number] => 11968840 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968840
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Jan 2, 2008 Abandoned
Array ( [id] => 4849456 [patent_doc_number] => 20080315198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/967380 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315198.pdf [firstpage_image] =>[orig_patent_app_number] => 11967380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967380
IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME Dec 30, 2007 Abandoned
Array ( [id] => 5432266 [patent_doc_number] => 20090166852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR PACKAGES WITH THERMAL INTERFACE MATERIALS' [patent_app_type] => utility [patent_app_number] => 11/967860 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166852.pdf [firstpage_image] =>[orig_patent_app_number] => 11967860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967860
SEMICONDUCTOR PACKAGES WITH THERMAL INTERFACE MATERIALS Dec 30, 2007 Abandoned
Array ( [id] => 5432240 [patent_doc_number] => 20090166826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'LEAD FRAME DIE ATTACH PADDLES WITH SLOPED WALLS AND BACKSIDE GROOVES SUITABLE FOR LEADLESS PACKAGES' [patent_app_type] => utility [patent_app_number] => 11/965620 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5415 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166826.pdf [firstpage_image] =>[orig_patent_app_number] => 11965620 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965620
LEAD FRAME DIE ATTACH PADDLES WITH SLOPED WALLS AND BACKSIDE GROOVES SUITABLE FOR LEADLESS PACKAGES Dec 26, 2007 Abandoned
Array ( [id] => 4876725 [patent_doc_number] => 20080150108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/964460 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150108.pdf [firstpage_image] =>[orig_patent_app_number] => 11964460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964460
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME Dec 25, 2007 Abandoned
Array ( [id] => 5499357 [patent_doc_number] => 20090160045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'WAFER LEVEL CHIP SCALE PACKAGING' [patent_app_type] => utility [patent_app_number] => 11/963690 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2672 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160045.pdf [firstpage_image] =>[orig_patent_app_number] => 11963690 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963690
Wafer level chip scale packaging Dec 20, 2007 Issued
Array ( [id] => 8760605 [patent_doc_number] => 08421128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Semiconductor device heat dissipation structure' [patent_app_type] => utility [patent_app_number] => 11/960030 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7726 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11960030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960030
Semiconductor device heat dissipation structure Dec 18, 2007 Issued
Array ( [id] => 5499365 [patent_doc_number] => 20090160053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCOTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/959995 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4685 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160053.pdf [firstpage_image] =>[orig_patent_app_number] => 11959995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959995
METHOD OF MANUFACTURING A SEMICONDUCOTOR DEVICE Dec 18, 2007 Abandoned
Array ( [id] => 5282287 [patent_doc_number] => 20090095961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Combination of LED and heat dissipation device' [patent_app_type] => utility [patent_app_number] => 11/987820 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1636 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20090095961.pdf [firstpage_image] =>[orig_patent_app_number] => 11987820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987820
Combination of LED and heat dissipation device Dec 4, 2007 Abandoned
Array ( [id] => 4820847 [patent_doc_number] => 20080122104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Damascene interconnect structure having air gaps between metal lines and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/998030 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2103 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122104.pdf [firstpage_image] =>[orig_patent_app_number] => 11998030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/998030
Damascene interconnect structure having air gaps between metal lines and method for fabricating the same Nov 26, 2007 Abandoned
Array ( [id] => 5563224 [patent_doc_number] => 20090136076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Portable inflatable and illuminative speaker' [patent_app_type] => utility [patent_app_number] => 11/984913 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3041 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20090136076.pdf [firstpage_image] =>[orig_patent_app_number] => 11984913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984913
Portable inflatable and illuminative speaker Nov 25, 2007 Abandoned
Array ( [id] => 4829480 [patent_doc_number] => 20080128911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Semiconductor package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/984070 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3925 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128911.pdf [firstpage_image] =>[orig_patent_app_number] => 11984070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984070
Semiconductor package and method for manufacturing the same Nov 12, 2007 Abandoned
Array ( [id] => 4856561 [patent_doc_number] => 20080265411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Structure of packaging substrate and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/979980 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2986 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265411.pdf [firstpage_image] =>[orig_patent_app_number] => 11979980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/979980
Structure of packaging substrate and method for making the same Nov 12, 2007 Abandoned
Array ( [id] => 5262354 [patent_doc_number] => 20090115039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'High Bond Line Thickness For Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 11/935915 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2736 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115039.pdf [firstpage_image] =>[orig_patent_app_number] => 11935915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935915
High bond line thickness for semiconductor devices Nov 5, 2007 Issued
Array ( [id] => 5262341 [patent_doc_number] => 20090115026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIAS FOR HIGH CURRENT,HIGH FREQUENCY, AND HEAT DISSIPATION' [patent_app_type] => utility [patent_app_number] => 11/934860 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4359 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115026.pdf [firstpage_image] =>[orig_patent_app_number] => 11934860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934860
SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIAS FOR HIGH CURRENT,HIGH FREQUENCY, AND HEAT DISSIPATION Nov 4, 2007 Abandoned
Array ( [id] => 4640023 [patent_doc_number] => 08018050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Integrated circuit package with integrated heat sink' [patent_app_type] => utility [patent_app_number] => 11/933990 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4794 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/018/08018050.pdf [firstpage_image] =>[orig_patent_app_number] => 11933990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933990
Integrated circuit package with integrated heat sink Oct 31, 2007 Issued
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