Search

Jack S. J. Chen

Examiner (ID: 8129, Phone: (571)272-1689 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2813, 2893
Total Applications
1826
Issued Applications
1467
Pending Applications
139
Abandoned Applications
265

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18520820 [patent_doc_number] => 11710715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/208005 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/208005
Semiconductor package Mar 21, 2021 Issued
Array ( [id] => 18625658 [patent_doc_number] => 11758725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Memory device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/204416 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 9561 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204416
Memory device and manufacturing method thereof Mar 16, 2021 Issued
Array ( [id] => 18402167 [patent_doc_number] => 11664315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Structure with interconnection die and method of making same [patent_app_type] => utility [patent_app_number] => 17/199412 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 11372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199412
Structure with interconnection die and method of making same Mar 10, 2021 Issued
Array ( [id] => 17126627 [patent_doc_number] => 20210301396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/198604 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198604
Method of processing substrate, substrate processing apparatus, recording medium, and method of manufacturing semiconductor device Mar 10, 2021 Issued
Array ( [id] => 17262777 [patent_doc_number] => 20210375762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING DIFFERENT ARCHITECTURES AND SEMICONDUCTOR DEVICES FABRICATED THEREBY [patent_app_type] => utility [patent_app_number] => 17/196240 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196240
Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby Mar 8, 2021 Issued
Array ( [id] => 19670917 [patent_doc_number] => 12183688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Integrated circuit die package stiffeners of metal alloys having exceptionally high CTE [patent_app_type] => utility [patent_app_number] => 17/192770 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5902 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192770
Integrated circuit die package stiffeners of metal alloys having exceptionally high CTE Mar 3, 2021 Issued
Array ( [id] => 17110631 [patent_doc_number] => 20210291228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MICROFABRICATED ULTRASONIC TRANSDUCER HAVING INDIVIDUAL CELLS WITH ELECTRICALLY ISOLATED ELECTRODE SECTIONS [patent_app_type] => utility [patent_app_number] => 17/192700 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192700
Microfabricated ultrasonic transducer having individual cells with electrically isolated electrode sections Mar 3, 2021 Issued
Array ( [id] => 16888907 [patent_doc_number] => 20210175104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => ADAPTIVE CONTROL OF VARIABILITY IN DEVICE PERFORMANCE IN ADVANCED SEMICONDUCTOR PROCESSES [patent_app_type] => utility [patent_app_number] => 17/182119 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182119
Adaptive control of variability in device performance in advanced semiconductor processes Feb 21, 2021 Issued
Array ( [id] => 18563020 [patent_doc_number] => 11728273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Bonded structure with interconnect structure [patent_app_type] => utility [patent_app_number] => 17/171351 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7651 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171351 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171351
Bonded structure with interconnect structure Feb 8, 2021 Issued
Array ( [id] => 20268747 [patent_doc_number] => 12439763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Electrically gated nanostructure devices [patent_app_type] => utility [patent_app_number] => 17/170685 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12458 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170685
Electrically gated nanostructure devices Feb 7, 2021 Issued
Array ( [id] => 17217777 [patent_doc_number] => 20210351115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/166305 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166305
ELECTRONIC DEVICE Feb 2, 2021 Abandoned
Array ( [id] => 18331819 [patent_doc_number] => 11637075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Semiconductor device having three-dimensional structure [patent_app_type] => utility [patent_app_number] => 17/163891 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163891
Semiconductor device having three-dimensional structure Jan 31, 2021 Issued
Array ( [id] => 18073748 [patent_doc_number] => 11532588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Copper paste for pressureless bonding, bonded body and semiconductor device [patent_app_type] => utility [patent_app_number] => 17/153993 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15451 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17153993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/153993
Copper paste for pressureless bonding, bonded body and semiconductor device Jan 20, 2021 Issued
Array ( [id] => 17456121 [patent_doc_number] => 11270988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => 3D semiconductor device(s) and structure(s) with electronic control units [patent_app_type] => utility [patent_app_number] => 17/151867 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 57 [patent_no_of_words] => 17624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151867
3D semiconductor device(s) and structure(s) with electronic control units Jan 18, 2021 Issued
Array ( [id] => 17752948 [patent_doc_number] => 20220231153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => CMOS Fabrication Methods for Back-Gate Transistor [patent_app_type] => utility [patent_app_number] => 17/150658 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150658
CMOS fabrication methods for back-gate transistor Jan 14, 2021 Issued
Array ( [id] => 17862920 [patent_doc_number] => 11444081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Integrated circuit (IC) device [patent_app_type] => utility [patent_app_number] => 17/150712 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 13262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150712
Integrated circuit (IC) device Jan 14, 2021 Issued
Array ( [id] => 18131406 [patent_doc_number] => 11557623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Image pickup element, method of manufacturing image pickup element, and electronic apparatus [patent_app_type] => utility [patent_app_number] => 17/145488 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8029 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145488
Image pickup element, method of manufacturing image pickup element, and electronic apparatus Jan 10, 2021 Issued
Array ( [id] => 18623826 [patent_doc_number] => 11756882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor die with blast shielding [patent_app_type] => utility [patent_app_number] => 17/138906 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8778 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138906
Semiconductor die with blast shielding Dec 30, 2020 Issued
Array ( [id] => 18024316 [patent_doc_number] => 20220375815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Semiconductor Package and Method for Manufacturing the Same [patent_app_type] => utility [patent_app_number] => 17/259938 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17259938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/259938
Semiconductor package and method for manufacturing the same Dec 27, 2020 Issued
Array ( [id] => 16765496 [patent_doc_number] => 20210111078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => FABRICATION OF SILICON GERMANIUM CHANNEL AND SILICON/SILICON GERMANIUM DUAL CHANNEL FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/132253 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132253
FABRICATION OF SILICON GERMANIUM CHANNEL AND SILICON/SILICON GERMANIUM DUAL CHANNEL FIELD-EFFECT TRANSISTORS Dec 22, 2020 Pending
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