
Jack S. J. Chen
Examiner (ID: 1643, Phone: (571)272-1689 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2893, 2813 |
| Total Applications | 1864 |
| Issued Applications | 1486 |
| Pending Applications | 133 |
| Abandoned Applications | 267 |
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|---|---|---|---|
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