Search

Jack S. J. Chen

Examiner (ID: 8129, Phone: (571)272-1689 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2813, 2893
Total Applications
1826
Issued Applications
1467
Pending Applications
139
Abandoned Applications
265

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17360108 [patent_doc_number] => 20220020904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => OPTOELECTRONIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/414861 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17414861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/414861
Optoelectronic light emitting device and manufacturing method Dec 16, 2019 Issued
Array ( [id] => 20246172 [patent_doc_number] => 12426518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Conductive oxide diffusion barrier for laser crystallization [patent_app_type] => utility [patent_app_number] => 16/718077 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718077
Conductive oxide diffusion barrier for laser crystallization Dec 16, 2019 Issued
Array ( [id] => 18426118 [patent_doc_number] => 20230180583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => OLED DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/966178 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16966178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/966178
OLED display panel Dec 15, 2019 Issued
Array ( [id] => 15776115 [patent_doc_number] => 20200119075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/714137 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714137
Semiconductor device and method for production of semiconductor device Dec 12, 2019 Issued
Array ( [id] => 17270363 [patent_doc_number] => 11195791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Method for forming semiconductor contact structure [patent_app_type] => utility [patent_app_number] => 16/707301 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707301 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707301
Method for forming semiconductor contact structure Dec 8, 2019 Issued
Array ( [id] => 17373975 [patent_doc_number] => 20220029027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => Multiple-Gate Transistor [patent_app_type] => utility [patent_app_number] => 17/298323 [patent_app_country] => US [patent_app_date] => 2019-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17298323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/298323
Multiple-gate transistor Nov 28, 2019 Issued
Array ( [id] => 20332856 [patent_doc_number] => 12463141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor substrate, semiconductor package, method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/694857 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 912 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694857
Semiconductor substrate, semiconductor package, method of manufacturing the same Nov 24, 2019 Issued
Array ( [id] => 17224855 [patent_doc_number] => 11177365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Semiconductor device with adhesion layer [patent_app_type] => utility [patent_app_number] => 16/695006 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695006
Semiconductor device with adhesion layer Nov 24, 2019 Issued
Array ( [id] => 15688455 [patent_doc_number] => 20200098891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SEMICONDUCTOR DEVICE WITH ADHESION LAYER AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 16/694971 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694971
Semiconductor device with adhesion layer and method of making Nov 24, 2019 Issued
Array ( [id] => 18120555 [patent_doc_number] => 11551954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Advanced process control system [patent_app_type] => utility [patent_app_number] => 16/691519 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2491 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691519 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/691519
Advanced process control system Nov 20, 2019 Issued
Array ( [id] => 17339446 [patent_doc_number] => 20220005777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => SEMICONDUCTOR ASSEMBLY WITH DISCRETE ENERGY STORAGE COMPONENT [patent_app_type] => utility [patent_app_number] => 17/289060 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17289060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/289060
SEMICONDUCTOR ASSEMBLY WITH DISCRETE ENERGY STORAGE COMPONENT Nov 19, 2019 Abandoned
Array ( [id] => 15657047 [patent_doc_number] => 20200091054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/683424 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683424 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683424
Fan-out semiconductor package Nov 13, 2019 Issued
Array ( [id] => 16536460 [patent_doc_number] => 10879073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Insulating gate separation structure for transistor devices [patent_app_type] => utility [patent_app_number] => 16/679829 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679829
Insulating gate separation structure for transistor devices Nov 10, 2019 Issued
Array ( [id] => 15587343 [patent_doc_number] => 20200070206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => MICROFABRICATED ULTRASONIC TRANSDUCER HAVING INDIVIDUAL CELLS WITH ELECTRICALLY ISOLATED ELECTRODE SECTIONS [patent_app_type] => utility [patent_app_number] => 16/679500 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679500
Microfabricated ultrasonic transducer having individual cells with electrically isolated electrode sections Nov 10, 2019 Issued
Array ( [id] => 15597983 [patent_doc_number] => 20200075526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/676439 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676439
Package structure and method of manufacturing the same Nov 6, 2019 Issued
Array ( [id] => 16796045 [patent_doc_number] => 20210125862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SUPER VIA INTEGRATION IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/664677 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664677
SUPER VIA INTEGRATION IN INTEGRATED CIRCUITS Oct 24, 2019 Abandoned
Array ( [id] => 15840541 [patent_doc_number] => 20200135553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/664317 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664317
Method of manufacturing semiconductor devices including formation of adhesion enhancement layer Oct 24, 2019 Issued
Array ( [id] => 15869731 [patent_doc_number] => 20200142269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/664238 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664238
Display device Oct 24, 2019 Issued
Array ( [id] => 15840807 [patent_doc_number] => 20200135686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR DIE WITH MULTIPLE CONTACT PADS ELECTRICALLY COUPLED TO A LEAD OF A LEAD FRAME [patent_app_type] => utility [patent_app_number] => 16/664568 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664568
Semiconductor die with multiple contact pads electrically coupled to a lead of a lead frame Oct 24, 2019 Issued
Array ( [id] => 16348150 [patent_doc_number] => 20200312801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/663735 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663735 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663735
Semiconductor package substrate and method of manufacturing semiconductor package using the same Oct 24, 2019 Issued
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