Search

Jack S. J. Chen

Examiner (ID: 8129, Phone: (571)272-1689 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2813, 2893
Total Applications
1826
Issued Applications
1467
Pending Applications
139
Abandoned Applications
265

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19488843 [patent_doc_number] => 12108586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Two-port SRAM structure [patent_app_type] => utility [patent_app_number] => 18/320321 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320321
Two-port SRAM structure May 18, 2023 Issued
Array ( [id] => 19399731 [patent_doc_number] => 12074119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Chip package structure [patent_app_type] => utility [patent_app_number] => 18/319610 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319610
Chip package structure May 17, 2023 Issued
Array ( [id] => 19016417 [patent_doc_number] => 11923362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Integrated circuit (IC) device [patent_app_type] => utility [patent_app_number] => 18/314569 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 13291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314569
Integrated circuit (IC) device May 8, 2023 Issued
Array ( [id] => 18586068 [patent_doc_number] => 20230268333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/140917 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/140917
Semiconductor devices Apr 27, 2023 Issued
Array ( [id] => 18584999 [patent_doc_number] => 20230267263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => Space Optimization Between SRAM Cells and Standard Cells [patent_app_type] => utility [patent_app_number] => 18/308860 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308860
Space Optimization Between SRAM Cells and Standard Cells Apr 27, 2023 Pending
Array ( [id] => 18570578 [patent_doc_number] => 20230260915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 18/303589 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303589 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303589
SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME Apr 19, 2023 Pending
Array ( [id] => 18757625 [patent_doc_number] => 20230361088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => POWER SEMICONDUCTOR PACKAGE HAVING FIRST AND SECOND LEAD FRAMES [patent_app_type] => utility [patent_app_number] => 18/130952 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18130952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/130952
Power semiconductor package having first and second lead frames Apr 4, 2023 Issued
Array ( [id] => 18542699 [patent_doc_number] => 20230247817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => METHOD OF MAKING SEMICONDUCTOR DEVICE WHICH INCLUDES FINS [patent_app_type] => utility [patent_app_number] => 18/190670 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190670
METHOD OF MAKING SEMICONDUCTOR DEVICE WHICH INCLUDES FINS Mar 26, 2023
Array ( [id] => 19030007 [patent_doc_number] => 11929376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Solid-state imaging device and imaging apparatus [patent_app_type] => utility [patent_app_number] => 18/184295 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9798 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184295
Solid-state imaging device and imaging apparatus Mar 14, 2023 Issued
Array ( [id] => 18442202 [patent_doc_number] => 20230189498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/106448 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/106448
Semiconductor device Feb 5, 2023 Issued
Array ( [id] => 18437612 [patent_doc_number] => 20230184907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => HIGH-SPEED LIGHT SENSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/105432 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105432
High-speed light sensing apparatus Feb 2, 2023 Issued
Array ( [id] => 18723347 [patent_doc_number] => 11800725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-24 [patent_title] => 3D semiconductor devices and structures with electronic circuit units [patent_app_type] => utility [patent_app_number] => 18/104299 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 57 [patent_no_of_words] => 19226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104299 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104299
3D semiconductor devices and structures with electronic circuit units Jan 31, 2023 Issued
Array ( [id] => 18774434 [patent_doc_number] => 20230369265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => FILM PACKAGE AND PACKAGE MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/100859 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100859
FILM PACKAGE AND PACKAGE MODULE INCLUDING THE SAME Jan 23, 2023 Pending
Array ( [id] => 18382091 [patent_doc_number] => 20230157182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/098091 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098091
Method for fabricating semiconductor device Jan 16, 2023 Issued
Array ( [id] => 18555262 [patent_doc_number] => 20230253279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/096914 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096914
Semiconductor device and method of manufacturing a semiconductor device Jan 12, 2023 Issued
Array ( [id] => 19285785 [patent_doc_number] => 20240222262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/150192 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150192
SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF Jan 3, 2023 Pending
Array ( [id] => 18360796 [patent_doc_number] => 20230142387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => WAVEGUIDE DUAL-DEPLETION REGION (DDR) PHOTODIODES [patent_app_type] => utility [patent_app_number] => 18/092286 [patent_app_country] => US [patent_app_date] => 2022-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092286 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092286
WAVEGUIDE DUAL-DEPLETION REGION (DDR) PHOTODIODES Dec 30, 2022 Pending
Array ( [id] => 20334555 [patent_doc_number] => 12464852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Waveguide dual-depletion region (DDR) photodiodes [patent_app_type] => utility [patent_app_number] => 18/092305 [patent_app_country] => US [patent_app_date] => 2022-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092305
Waveguide dual-depletion region (DDR) photodiodes Dec 30, 2022 Issued
Array ( [id] => 18334600 [patent_doc_number] => 20230126548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/145221 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145221 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145221
Solid-state imaging device and electronic apparatus Dec 21, 2022 Issued
Array ( [id] => 18322991 [patent_doc_number] => 20230121119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE [patent_app_type] => utility [patent_app_number] => 18/068718 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068718
Method of making a semiconductor device using a dummy gate Dec 19, 2022 Issued
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