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Jacob Andrew Petranek

Examiner (ID: 8886, Phone: (571)272-5988 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1019
Issued Applications
761
Pending Applications
76
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20556954 [patent_doc_number] => 20260056739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => Large Systolic Arrays in AI Processors [patent_app_type] => utility [patent_app_number] => 19/277292 [patent_app_country] => US [patent_app_date] => 2025-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19277292 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/277292
Large Systolic Arrays in AI Processors Jul 21, 2025 Pending
Array ( [id] => 20166626 [patent_doc_number] => 20250258673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => Hardware Verification of Dynamically Generated Code [patent_app_type] => utility [patent_app_number] => 19/170976 [patent_app_country] => US [patent_app_date] => 2025-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19170976 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/170976
Hardware Verification of Dynamically Generated Code Apr 3, 2025 Pending
Array ( [id] => 20281683 [patent_doc_number] => 20250306925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Structured Sparse Matrix Acceleration In Systolic Arrays [patent_app_type] => utility [patent_app_number] => 19/097425 [patent_app_country] => US [patent_app_date] => 2025-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19097425 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/097425
Structured Sparse Matrix Acceleration In Systolic Arrays Mar 31, 2025 Pending
Array ( [id] => 20513214 [patent_doc_number] => 20260037315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => AI ACCELERATOR, SoC AND ELECTRIC DEVICE INCLUDING AI ACCELERATOR, AND OPERATING METHOD OF AI ACCELERATOR [patent_app_type] => utility [patent_app_number] => 19/092507 [patent_app_country] => US [patent_app_date] => 2025-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19092507 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/092507
AI ACCELERATOR, SoC AND ELECTRIC DEVICE INCLUDING AI ACCELERATOR, AND OPERATING METHOD OF AI ACCELERATOR Mar 26, 2025 Pending
Array ( [id] => 20281702 [patent_doc_number] => 20250306944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => VECTOR OPERATION SEQUENCING FOR EXCEPTION HANDLING [patent_app_type] => utility [patent_app_number] => 19/090558 [patent_app_country] => US [patent_app_date] => 2025-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19090558 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/090558
VECTOR OPERATION SEQUENCING FOR EXCEPTION HANDLING Mar 25, 2025 Pending
Array ( [id] => 20138142 [patent_doc_number] => 20250245186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES [patent_app_type] => utility [patent_app_number] => 19/075311 [patent_app_country] => US [patent_app_date] => 2025-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19075311 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/075311
OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES Mar 9, 2025 Pending
Array ( [id] => 20087223 [patent_doc_number] => 20250217159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MESSAGE-BASED PROCESSING WITH ASSIGNMENT OF NEURAL NETWORK LAYERS TO PROCESSOR CLUSTERS [patent_app_type] => utility [patent_app_number] => 19/065949 [patent_app_country] => US [patent_app_date] => 2025-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19065949 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/065949
MESSAGE-BASED PROCESSING WITH ASSIGNMENT OF NEURAL NETWORK LAYERS TO PROCESSOR CLUSTERS Feb 26, 2025 Pending
Array ( [id] => 20181129 [patent_doc_number] => 20250265087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => Machine-Learned Model Alignment With Synthetic Data [patent_app_type] => utility [patent_app_number] => 19/055348 [patent_app_country] => US [patent_app_date] => 2025-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19055348 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/055348
Machine-Learned Model Alignment With Synthetic Data Feb 16, 2025 Pending
Array ( [id] => 20034910 [patent_doc_number] => 20250173132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => CREDIT-BASED ARBITRATION FOR A RECONFIGURABLE DATA PROCESSOR [patent_app_type] => utility [patent_app_number] => 19/038730 [patent_app_country] => US [patent_app_date] => 2025-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038730 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/038730
CREDIT-BASED ARBITRATION FOR A RECONFIGURABLE DATA PROCESSOR Jan 27, 2025 Pending
Array ( [id] => 20296493 [patent_doc_number] => 20250321736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 19/029095 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19029095 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/029095
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE Jan 16, 2025 Pending
Array ( [id] => 20027034 [patent_doc_number] => 20250165256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEPARATE BRANCH TARGET BUFFERS FOR DIFFERENT LEVELS OF CALLS [patent_app_type] => utility [patent_app_number] => 19/023081 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023081 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/023081
SEPARATE BRANCH TARGET BUFFERS FOR DIFFERENT LEVELS OF CALLS Jan 14, 2025 Pending
Array ( [id] => 20281691 [patent_doc_number] => 20250306933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SIMULATION APPARATUS, SIMULATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/021511 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19021511 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/021511
SIMULATION APPARATUS, SIMULATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM Jan 14, 2025 Pending
Array ( [id] => 20152238 [patent_doc_number] => 20250252076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SYSTOLIC ARRAY, PROCESSING CIRCUIT INCLUDING SYSTOLIC ARRAY, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 19/014441 [patent_app_country] => US [patent_app_date] => 2025-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19014441 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/014441
SYSTOLIC ARRAY, PROCESSING CIRCUIT INCLUDING SYSTOLIC ARRAY, AND ELECTRONIC DEVICE Jan 8, 2025 Pending
Array ( [id] => 19891907 [patent_doc_number] => 20250117219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => NEURAL PROCESSING DEVICE, PROCESSING ELEMENT INCLUDED THEREIN AND METHOD FOR OPERATING VARIOUS FORMATS OF NEURAL PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/988708 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/988708
NEURAL PROCESSING DEVICE, PROCESSING ELEMENT INCLUDED THEREIN AND METHOD FOR OPERATING VARIOUS FORMATS OF NEURAL PROCESSING DEVICE Dec 18, 2024 Pending
Array ( [id] => 19878479 [patent_doc_number] => 20250110736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 18/979355 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979355
PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING Dec 11, 2024 Pending
Array ( [id] => 20764429 [patent_doc_number] => 20260161413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-11 [patent_title] => PERFORMING TENSOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/974643 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/974643
PERFORMING TENSOR INSTRUCTIONS Dec 8, 2024 Pending
Array ( [id] => 19864545 [patent_doc_number] => 20250103331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => PROCESSOR EMBEDDED STREAMING BUFFER [patent_app_type] => utility [patent_app_number] => 18/971447 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971447
PROCESSOR EMBEDDED STREAMING BUFFER Dec 5, 2024 Pending
Array ( [id] => 20035060 [patent_doc_number] => 20250173282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING METHOD OF HOST DEVICE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/960101 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960101
MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING METHOD OF HOST DEVICE FOR MEMORY DEVICE Nov 25, 2024 Pending
Array ( [id] => 20673187 [patent_doc_number] => 12613699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => DMA controller and LSU to transpose data arrays stored in main memory for storage in processor registers [patent_app_type] => utility [patent_app_number] => 18/956439 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 609 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18956439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/956439
DMA controller and LSU to transpose data arrays stored in main memory for storage in processor registers Nov 21, 2024 Issued
Array ( [id] => 20351467 [patent_doc_number] => 20250348319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => Instruction Caching Scheme for High Performance RISC Processors [patent_app_type] => utility [patent_app_number] => 18/951978 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18951978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/951978
Instruction Caching Scheme for High Performance RISC Processors Nov 18, 2024 Pending
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