Search

Jacob Andrew Petranek

Examiner (ID: 8886, Phone: (571)272-5988 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1019
Issued Applications
761
Pending Applications
76
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17771312 [patent_doc_number] => 11403255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Managing discovered chiplets based on physical topology [patent_app_type] => utility [patent_app_number] => 17/361655 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361655
Managing discovered chiplets based on physical topology Jun 28, 2021 Issued
Array ( [id] => 18686970 [patent_doc_number] => 11782706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-10 [patent_title] => Reconfigurable neural network processing based on subgraph recognition [patent_app_type] => utility [patent_app_number] => 17/361992 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361992
Reconfigurable neural network processing based on subgraph recognition Jun 28, 2021 Issued
Array ( [id] => 17853771 [patent_doc_number] => 20220283813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => FLEXIBLE RETURN AND EVENT DELIVERY [patent_app_type] => utility [patent_app_number] => 17/359534 [patent_app_country] => US [patent_app_date] => 2021-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359534
FLEXIBLE RETURN AND EVENT DELIVERY Jun 25, 2021 Pending
Array ( [id] => 18095518 [patent_doc_number] => 20220413859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SYSTEM, APPARATUS AND METHODS FOR PERFORMANT READ AND WRITE OF PROCESSOR STATE INFORMATION RESPONSIVE TO LIST INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/358082 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358082
System, apparatus and methods for performant read and write of processor state information responsive to list instructions Jun 24, 2021 Issued
Array ( [id] => 18095511 [patent_doc_number] => 20220413852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => PROCESSOR EMBEDDED STREAMING BUFFER [patent_app_type] => utility [patent_app_number] => 17/358218 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358218
Processor embedded streaming buffer Jun 24, 2021 Issued
Array ( [id] => 17581113 [patent_doc_number] => 20220137968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => Hardware Verification of Dynamically Generated Code [patent_app_type] => utility [patent_app_number] => 17/348565 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348565
Hardware verification of dynamically generated code Jun 14, 2021 Issued
Array ( [id] => 18651551 [patent_doc_number] => 20230297387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => CALCULATION APPARATUS, INTEGRATED CIRCUIT CHIP, BOARD CARD, ELECTRONIC DEVICE AND CALCULATION METHOD [patent_app_type] => utility [patent_app_number] => 18/013589 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18013589 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/013589
CALCULATION APPARATUS, INTEGRATED CIRCUIT CHIP, BOARD CARD, ELECTRONIC DEVICE AND CALCULATION METHOD May 18, 2021 Pending
Array ( [id] => 17846639 [patent_doc_number] => 11436012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Automated orchestration of large-scale flow log transformation [patent_app_type] => utility [patent_app_number] => 17/321175 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321175 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321175
Automated orchestration of large-scale flow log transformation May 13, 2021 Issued
Array ( [id] => 17984611 [patent_doc_number] => 20220350648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => WORK SCHEDULING ON PROCESSING UNITS [patent_app_type] => utility [patent_app_number] => 17/245569 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245569
Work scheduling on candidate collections of processing units selected according to a criterion Apr 29, 2021 Issued
Array ( [id] => 17962133 [patent_doc_number] => 20220342714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => METHOD AND SYSTEM FOR PROVISIONING WORKFLOWS WITH DYNAMIC ACCELERATOR POOLS [patent_app_type] => utility [patent_app_number] => 17/236733 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236733 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236733
METHOD AND SYSTEM FOR PROVISIONING WORKFLOWS WITH DYNAMIC ACCELERATOR POOLS Apr 20, 2021 Abandoned
Array ( [id] => 18154788 [patent_doc_number] => 11567766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Control registers to store thread identifiers for threaded loop execution in a self-scheduling reconfigurable computing fabric [patent_app_type] => utility [patent_app_number] => 17/227333 [patent_app_country] => US [patent_app_date] => 2021-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 31732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227333
Control registers to store thread identifiers for threaded loop execution in a self-scheduling reconfigurable computing fabric Apr 10, 2021 Issued
Array ( [id] => 17157933 [patent_doc_number] => 20210318984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => PROCESSOR, SYSTEM ON CHIP INCLUDING HETEROGENEOUS CORE, AND OPERATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/224628 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224628
Processor, system on chip including heterogeneous core, and operating methods thereof for optimizing hot functions for execution on each core of a heterogeneous processor Apr 6, 2021 Issued
Array ( [id] => 18750556 [patent_doc_number] => 11809870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor [patent_app_type] => utility [patent_app_number] => 17/224373 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 10869 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224373
Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor Apr 6, 2021 Issued
Array ( [id] => 17565176 [patent_doc_number] => 20220129325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => PARALLELIZATION METHOD AND APPARATUS WITH PROCESSING OF NEURAL NETWORK MODEL FOR MANYCORE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/224428 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224428
Parallelization method and apparatus with processing of neural network model for manycore system Apr 6, 2021 Issued
Array ( [id] => 16979831 [patent_doc_number] => 20210224068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Execution Control of a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 17/221992 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221992
Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric Apr 4, 2021 Issued
Array ( [id] => 17682529 [patent_doc_number] => 11366783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-21 [patent_title] => Multi-headed multi-buffer for buffering data for processing [patent_app_type] => utility [patent_app_number] => 17/216650 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 18250 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216650 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216650
Multi-headed multi-buffer for buffering data for processing Mar 28, 2021 Issued
Array ( [id] => 17899368 [patent_doc_number] => 20220309030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SYSTEM AND METHOD FOR DATA-LAYOUT AWARE DECOMPRESSION AND VERIFICATION USING A HARDWARE ACCELERATOR CHAIN [patent_app_type] => utility [patent_app_number] => 17/215122 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215122
System and method for data-layout aware decompression and verification using a hardware accelerator chain Mar 28, 2021 Issued
Array ( [id] => 19443422 [patent_doc_number] => 12093694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders [patent_app_type] => utility [patent_app_number] => 17/214693 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 31704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214693
Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders Mar 25, 2021 Issued
Array ( [id] => 17955153 [patent_doc_number] => 11481258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Detecting real-time clock loss [patent_app_type] => utility [patent_app_number] => 17/212813 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 16500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212813
Detecting real-time clock loss Mar 24, 2021 Issued
Array ( [id] => 17915617 [patent_doc_number] => 20220318013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/212588 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212588
Supporting 8-bit floating point format operands in a computing architecture Mar 24, 2021 Issued
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