Search

Jacob Andrew Petranek

Examiner (ID: 8886, Phone: (571)272-5988 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1019
Issued Applications
761
Pending Applications
76
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16964812 [patent_doc_number] => 20210216311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => ARITHMETIC AND LOGICAL OPERATIONS IN A MULTI-USER NETWORK [patent_app_type] => utility [patent_app_number] => 17/212115 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212115
Converting floating-point bit strings in a multi-user network Mar 24, 2021 Issued
Array ( [id] => 17651407 [patent_doc_number] => 11354134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Processing-in-memory implementations of parsing strings against context-free grammars [patent_app_type] => utility [patent_app_number] => 17/212551 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212551
Processing-in-memory implementations of parsing strings against context-free grammars Mar 24, 2021 Issued
Array ( [id] => 17899218 [patent_doc_number] => 20220308880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => DATA PROCESSING APPARATUS AND METHOD FOR PREFETCH GENERATION [patent_app_type] => utility [patent_app_number] => 17/209515 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209515 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209515
Data processing apparatus and method for generating prefetches based on a nested prefetch pattern Mar 22, 2021 Issued
Array ( [id] => 16979830 [patent_doc_number] => 20210224067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Backpressure Control Using a Stop Signal for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 17/200787 [patent_app_country] => US [patent_app_date] => 2021-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200787
Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric Mar 12, 2021 Issued
Array ( [id] => 17778605 [patent_doc_number] => 20220244955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => METHOD, SYSTEM FOR EDITING A COMMAND SET AND DEVICE APPLYING THE METHOD [patent_app_type] => utility [patent_app_number] => 17/162625 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162625
Method, system for editing a command set and device applying the method Jan 28, 2021 Issued
Array ( [id] => 18189305 [patent_doc_number] => 11579890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => Frame parser executing subsets of instructions in parallel for processing a frame header [patent_app_type] => utility [patent_app_number] => 17/161222 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161222 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161222
Frame parser executing subsets of instructions in parallel for processing a frame header Jan 27, 2021 Issued
Array ( [id] => 20416067 [patent_doc_number] => 12499354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Accelerating device, data processing system and operating method of accelerating device for performing calculation based on batch size and sequence size [patent_app_type] => utility [patent_app_number] => 17/161658 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6539 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161658
Accelerating device, data processing system and operating method of accelerating device for performing calculation based on batch size and sequence size Jan 27, 2021 Issued
Array ( [id] => 16856851 [patent_doc_number] => 20210157596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => Executing Memory Requests Out of Order [patent_app_type] => utility [patent_app_number] => 17/159019 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159019
Executing memory requests out of order Jan 25, 2021 Issued
Array ( [id] => 17621886 [patent_doc_number] => 11340942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Cooperative work-stealing scheduler [patent_app_type] => utility [patent_app_number] => 17/152021 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152021
Cooperative work-stealing scheduler Jan 18, 2021 Issued
Array ( [id] => 17736620 [patent_doc_number] => 20220222079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => CHANGE MANAGEMENT OF SERVICES DEPLOYED ON DATACENTERS CONFIGURED IN CLOUD PLATFORMS [patent_app_type] => utility [patent_app_number] => 17/148363 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148363
Change management of services deployed on datacenters configured in cloud platforms Jan 12, 2021 Issued
Array ( [id] => 19122352 [patent_doc_number] => 11966334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits [patent_app_type] => utility [patent_app_number] => 17/146440 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 17958 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146440
Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits Jan 10, 2021 Issued
Array ( [id] => 19678360 [patent_doc_number] => 12190224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Processing elements array that includes delay queues between processing elements to hold shared data [patent_app_type] => utility [patent_app_number] => 17/136744 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2828 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136744
Processing elements array that includes delay queues between processing elements to hold shared data Dec 28, 2020 Issued
Array ( [id] => 18933950 [patent_doc_number] => 11886378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Computer architecture with resistive processing units [patent_app_type] => utility [patent_app_number] => 17/135335 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135335
Computer architecture with resistive processing units Dec 27, 2020 Issued
Array ( [id] => 20317187 [patent_doc_number] => 12455738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Large-scale matrix restructuring and matrix-scalar operations [patent_app_type] => utility [patent_app_number] => 17/134251 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 47 [patent_no_of_words] => 20434 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134251
Large-scale matrix restructuring and matrix-scalar operations Dec 24, 2020 Issued
Array ( [id] => 18015072 [patent_doc_number] => 11507368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Spoofing a processor identification instruction [patent_app_type] => utility [patent_app_number] => 17/134249 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134249
Spoofing a processor identification instruction Dec 24, 2020 Issued
Array ( [id] => 17706785 [patent_doc_number] => 20220206791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHODS, SYSTEMS, AND APPARATUSES TO OPTIMIZE CROSS-LANE PACKED DATA INSTRUCTION IMPLEMENTATION ON A PARTIAL WIDTH PROCESSOR WITH A MINIMAL NUMBER OF MICRO-OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/134100 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134100
Methods, systems, and apparatuses to optimize cross-lane packed data instruction implementation on a partial width processor with a minimal number of micro-operations Dec 23, 2020 Issued
Array ( [id] => 18578075 [patent_doc_number] => 11734608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Address interleaving for machine learning [patent_app_type] => utility [patent_app_number] => 17/247810 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2995 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247810
Address interleaving for machine learning Dec 22, 2020 Issued
Array ( [id] => 20159991 [patent_doc_number] => 12386618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Multi-buffered register files with shared access circuits [patent_app_type] => utility [patent_app_number] => 17/132895 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4079 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132895
Multi-buffered register files with shared access circuits Dec 22, 2020 Issued
Array ( [id] => 17690347 [patent_doc_number] => 20220197640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => VECTOR PROCESSOR SUPPORTING LINEAR INTERPOLATION ON MULTIPLE DIMENSIONS [patent_app_type] => utility [patent_app_number] => 17/131939 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131939
Vector processor supporting linear interpolation on multiple dimensions Dec 22, 2020 Issued
Array ( [id] => 16780293 [patent_doc_number] => 20210117372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE TO MEMORY DATA WIDER THAN A NATIVELY SUPPORTED DATA WIDTH [patent_app_type] => utility [patent_app_number] => 17/131729 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131729
Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width Dec 21, 2020 Issued
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