| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 17230667
[patent_doc_number] => 20210357224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => DEFINING AND ACCESSING DYNAMIC REGISTERS IN A MULTI-PROCESSOR SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/874960
[patent_app_country] => US
[patent_app_date] => 2020-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874960
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/874960 | DEFINING AND ACCESSING DYNAMIC REGISTERS IN A MULTI-PROCESSOR SYSTEM | May 14, 2020 | Abandoned |
Array
(
[id] => 17817198
[patent_doc_number] => 11422809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-23
[patent_title] => Apparatus and method for multicasting a cache line update using delayed refetch messages
[patent_app_type] => utility
[patent_app_number] => 15/930887
[patent_app_country] => US
[patent_app_date] => 2020-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 17128
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930887
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/930887 | Apparatus and method for multicasting a cache line update using delayed refetch messages | May 12, 2020 | Issued |
Array
(
[id] => 17999523
[patent_doc_number] => 11500630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-15
[patent_title] => Apparatus and method for converting a floating-point value from half precision to single precision
[patent_app_type] => utility
[patent_app_number] => 16/872865
[patent_app_country] => US
[patent_app_date] => 2020-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 15189
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872865
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/872865 | Apparatus and method for converting a floating-point value from half precision to single precision | May 11, 2020 | Issued |
Array
(
[id] => 17187213
[patent_doc_number] => 20210334098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => Filtering Micro-Operations for a Micro-Operation Cache in a Processor
[patent_app_type] => utility
[patent_app_number] => 16/856832
[patent_app_country] => US
[patent_app_date] => 2020-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10952
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856832
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/856832 | Filtering micro-operations for a micro-operation cache in a processor | Apr 22, 2020 | Issued |
Array
(
[id] => 19493078
[patent_doc_number] => 12111789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Distributed graphics processor unit architecture
[patent_app_type] => utility
[patent_app_number] => 16/855879
[patent_app_country] => US
[patent_app_date] => 2020-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9565
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855879
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/855879 | Distributed graphics processor unit architecture | Apr 21, 2020 | Issued |
Array
(
[id] => 17172471
[patent_doc_number] => 20210326141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => MICROPROCESSOR WITH PIPELINE CONTROL FOR EXECUTING OF INSTRUCTION AT A PRESET FUTURE TIME
[patent_app_type] => utility
[patent_app_number] => 16/853717
[patent_app_country] => US
[patent_app_date] => 2020-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853717
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/853717 | Microprocessor with pipeline control for executing of instruction at a preset future time | Apr 19, 2020 | Issued |
Array
(
[id] => 16393187
[patent_doc_number] => 20200334128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-22
[patent_title] => Real-Time Tracing of Instruction Execution on a Processor
[patent_app_type] => utility
[patent_app_number] => 16/850100
[patent_app_country] => US
[patent_app_date] => 2020-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850100
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/850100 | Generation of trace messages including an instruction retirement count and a stall count | Apr 15, 2020 | Issued |
Array
(
[id] => 17159916
[patent_doc_number] => 20210320967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => Edge Server with Deep Learning Accelerator and Random Access Memory
[patent_app_type] => utility
[patent_app_number] => 16/845007
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17887
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845007
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/845007 | Edge Server with Deep Learning Accelerator and Random Access Memory | Apr 8, 2020 | Pending |
Array
(
[id] => 16178978
[patent_doc_number] => 20200225946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => APPARATUS AND METHODS RELATED TO MICROCODE INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 16/834794
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10432
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834794
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/834794 | Apparatus and methods related to microcode instructions indicating instruction types | Mar 29, 2020 | Issued |
Array
(
[id] => 18136117
[patent_doc_number] => 11561795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => Accumulating data values and storing in first and second storage devices
[patent_app_type] => utility
[patent_app_number] => 16/834833
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12326
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834833
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/834833 | Accumulating data values and storing in first and second storage devices | Mar 29, 2020 | Issued |
Array
(
[id] => 16314747
[patent_doc_number] => 20200293485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => ON DEMAND MULTIPLE HETEROGENEOUS MULTICORE PROCESSORS
[patent_app_type] => utility
[patent_app_number] => 16/818390
[patent_app_country] => US
[patent_app_date] => 2020-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4526
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818390
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/818390 | ON DEMAND MULTIPLE HETEROGENEOUS MULTICORE PROCESSORS | Mar 12, 2020 | Abandoned |
Array
(
[id] => 18088379
[patent_doc_number] => 11538518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-27
[patent_title] => Memory device to suspend ROM operation and a method of operating the memory device
[patent_app_type] => utility
[patent_app_number] => 16/815676
[patent_app_country] => US
[patent_app_date] => 2020-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10033
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815676
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/815676 | Memory device to suspend ROM operation and a method of operating the memory device | Mar 10, 2020 | Issued |
Array
(
[id] => 18703384
[patent_doc_number] => 11789895
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-17
[patent_title] => On-chip heterogeneous AI processor with distributed tasks queues allowing for parallel task execution
[patent_app_type] => utility
[patent_app_number] => 16/812817
[patent_app_country] => US
[patent_app_date] => 2020-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6884
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 361
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812817
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/812817 | On-chip heterogeneous AI processor with distributed tasks queues allowing for parallel task execution | Mar 8, 2020 | Issued |
Array
(
[id] => 18687133
[patent_doc_number] => 11782870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Configurable heterogeneous AI processor with distributed task queues allowing parallel task execution
[patent_app_type] => utility
[patent_app_number] => 16/812832
[patent_app_country] => US
[patent_app_date] => 2020-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7083
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 573
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812832
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/812832 | Configurable heterogeneous AI processor with distributed task queues allowing parallel task execution | Mar 8, 2020 | Issued |
Array
(
[id] => 16330747
[patent_doc_number] => 20200301713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREOF, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 16/793236
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9057
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793236
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793236 | Updating setting values in a print presetting and selectively applying the presetting updates to parts of print workflows | Feb 17, 2020 | Issued |
Array
(
[id] => 17238277
[patent_doc_number] => 11182156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Selectively changing arithmetic data types used in arithmetic execution of deep learning applications based on expressible ratio and fluctuation value comparisons to threshold values
[patent_app_type] => utility
[patent_app_number] => 16/744240
[patent_app_country] => US
[patent_app_date] => 2020-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 16880
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744240
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/744240 | Selectively changing arithmetic data types used in arithmetic execution of deep learning applications based on expressible ratio and fluctuation value comparisons to threshold values | Jan 15, 2020 | Issued |
Array
(
[id] => 17573333
[patent_doc_number] => 11321606
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-03
[patent_title] => Systems, apparatus, methods, and architectures for a neural network workflow to generate a hardware accelerator
[patent_app_type] => utility
[patent_app_number] => 16/744040
[patent_app_country] => US
[patent_app_date] => 2020-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 13285
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744040
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/744040 | Systems, apparatus, methods, and architectures for a neural network workflow to generate a hardware accelerator | Jan 14, 2020 | Issued |
Array
(
[id] => 18178190
[patent_doc_number] => 20230038919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => PROGRAMMABLE CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 17/758129
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7339
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17758129
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/758129 | Accelerator controller for inserting template microcode instructions into a microcode buffer to accelerate matrix operations | Jan 12, 2020 | Issued |
Array
(
[id] => 16577331
[patent_doc_number] => 20210011732
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => Matrix Data Reuse Techniques in Processing Systems
[patent_app_type] => utility
[patent_app_number] => 16/731035
[patent_app_country] => US
[patent_app_date] => 2019-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7970
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731035
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/731035 | Matrix data reuse techniques in multiply and accumulate units of processing system | Dec 30, 2019 | Issued |
Array
(
[id] => 16918669
[patent_doc_number] => 20210191761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => MATRIX DATA BROADCAST ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 16/729811
[patent_app_country] => US
[patent_app_date] => 2019-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11318
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729811
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/729811 | Matrix data broadcast architecture | Dec 29, 2019 | Issued |