Search

Jacob Andrew Petranek

Examiner (ID: 11149, Phone: (571)272-5988 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1000
Issued Applications
752
Pending Applications
69
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15714723 [patent_doc_number] => 20200104128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SPOOFING A PROCESSOR IDENTIFICATION INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/147699 [patent_app_country] => US [patent_app_date] => 2018-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147699
Spoofing a processor identification instruction Sep 28, 2018 Issued
Array ( [id] => 15714741 [patent_doc_number] => 20200104137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => APPARATUSES AND METHODS FOR DYNAMIC ASYMMETRIC SCALING OF BRANCH PREDICTOR TABLES [patent_app_type] => utility [patent_app_number] => 16/147670 [patent_app_country] => US [patent_app_date] => 2018-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147670
Apparatuses and methods for dynamic asymmetric scaling of branch predictor tables Sep 28, 2018 Issued
Array ( [id] => 15715845 [patent_doc_number] => 20200104690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => NEURAL PROCESSING UNIT (NPU) DIRECT MEMORY ACCESS (NDMA) HARDWARE PRE-PROCESSING AND POST-PROCESSING [patent_app_type] => utility [patent_app_number] => 16/147189 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147189
Neural processing unit (NPU) direct memory access (NDMA) hardware pre-processing and post-processing Sep 27, 2018 Issued
Array ( [id] => 13907531 [patent_doc_number] => 20190042970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => APPARATUS AND METHOD FOR A HYBRID CLASSICAL-QUANTUM PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/144828 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/144828
APPARATUS AND METHOD FOR A HYBRID CLASSICAL-QUANTUM PROCESSOR Sep 26, 2018 Abandoned
Array ( [id] => 18189298 [patent_doc_number] => 11579883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Systems and methods for performing horizontal tile operations [patent_app_type] => utility [patent_app_number] => 16/131382 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 50 [patent_no_of_words] => 26427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16131382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/131382
Systems and methods for performing horizontal tile operations Sep 13, 2018 Issued
Array ( [id] => 15622615 [patent_doc_number] => 20200081712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => ATOMIC OPERATIONS IN A LARGE SCALE DISTRIBUTED COMPUTING NETWORK [patent_app_type] => utility [patent_app_number] => 16/126504 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126504
Atomic operations in a large scale distributed computing network Sep 9, 2018 Issued
Array ( [id] => 15594259 [patent_doc_number] => 20200073664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => REGISTER SHARING MECHANISM [patent_app_type] => utility [patent_app_number] => 16/120226 [patent_app_country] => US [patent_app_date] => 2018-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120226 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/120226
Recompiling GPU code based on spill/fill instructions and number of stall cycles Aug 31, 2018 Issued
Array ( [id] => 14161879 [patent_doc_number] => 20190108042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => CONFIGURABLE DIGITAL SIGNAL PROCESSOR FRACTURING AND MACHINE LEARNING UTILIZING THE SAME [patent_app_type] => utility [patent_app_number] => 16/117529 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117529 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117529
DSP execution slice array to provide operands to multiple logic units Aug 29, 2018 Issued
Array ( [id] => 16818622 [patent_doc_number] => 11003448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => DSP slice configured to forward operands to associated DSP slices [patent_app_type] => utility [patent_app_number] => 16/116869 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7508 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116869
DSP slice configured to forward operands to associated DSP slices Aug 28, 2018 Issued
Array ( [id] => 15214627 [patent_doc_number] => 20190370000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => PROCESSOR CIRCUIT AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/109713 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109713
Load store dependency predictor using separate alias tables for store address instructions and store data instructions Aug 21, 2018 Issued
Array ( [id] => 15561401 [patent_doc_number] => 20200065112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => ASYMMETRIC SPECULATIVE/NONSPECULATIVE CONDITIONAL BRANCHING [patent_app_type] => utility [patent_app_number] => 16/109402 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109402 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109402
ASYMMETRIC SPECULATIVE/NONSPECULATIVE CONDITIONAL BRANCHING Aug 21, 2018 Abandoned
Array ( [id] => 16431406 [patent_doc_number] => 10831488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Computation engine with extract instructions to minimize memory access [patent_app_type] => utility [patent_app_number] => 16/105783 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6768 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105783
Computation engine with extract instructions to minimize memory access Aug 19, 2018 Issued
Array ( [id] => 17528565 [patent_doc_number] => 11301253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Branch prediction structure indexed based on return address popped from a call-return stack [patent_app_type] => utility [patent_app_number] => 16/100448 [patent_app_country] => US [patent_app_date] => 2018-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7033 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100448 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/100448
Branch prediction structure indexed based on return address popped from a call-return stack Aug 9, 2018 Issued
Array ( [id] => 16535163 [patent_doc_number] => 10877763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor [patent_app_type] => utility [patent_app_number] => 16/052751 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 14885 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052751
Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor Aug 1, 2018 Issued
Array ( [id] => 13568965 [patent_doc_number] => 20180336030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => REDUCING STALLING IN A SIMULTANEOUS MULTITHREADING PROCESSOR BY INSERTING THREAD SWITCHES FOR INSTRUCTIONS LIKELY TO STALL [patent_app_type] => utility [patent_app_number] => 16/049929 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049929
Reducing stalling in a simultaneous multithreading processor by inserting thread switches for instructions likely to stall Jul 30, 2018 Issued
Array ( [id] => 13556273 [patent_doc_number] => 20180329684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => EXECUTING PEFORM FLOATING POINT OPERATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/046491 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046491 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046491
Executing perform floating point operation instructions Jul 25, 2018 Issued
Array ( [id] => 18015133 [patent_doc_number] => 11507429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Neural network accelerator including bidirectional processing element array [patent_app_type] => utility [patent_app_number] => 16/038243 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7920 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038243
Neural network accelerator including bidirectional processing element array Jul 17, 2018 Issued
Array ( [id] => 15090327 [patent_doc_number] => 20190339974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Static Identifications in Object-based Memory Access [patent_app_type] => utility [patent_app_number] => 16/028840 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028840
Static identifications in object-based memory access Jul 5, 2018 Issued
Array ( [id] => 15090329 [patent_doc_number] => 20190339975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Separate Branch Target Buffers for Different Levels of Calls [patent_app_type] => utility [patent_app_number] => 16/029135 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029135
Separate branch target buffers for different levels of calls Jul 5, 2018 Issued
Array ( [id] => 15328411 [patent_doc_number] => 20200004535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => ACCELERATOR APPARATUS AND METHOD FOR DECODING AND DE-SERIALIZING BIT-PACKED DATA [patent_app_type] => utility [patent_app_number] => 16/024815 [patent_app_country] => US [patent_app_date] => 2018-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16024815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/024815
ACCELERATOR APPARATUS AND METHOD FOR DECODING AND DE-SERIALIZING BIT-PACKED DATA Jun 29, 2018 Abandoned
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