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Jacob Andrew Petranek

Examiner (ID: 11567, Phone: (571)272-5988 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1000
Issued Applications
751
Pending Applications
70
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19481944 [patent_doc_number] => 20240329986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => OPPORTUNISTIC WRITE-BACK DISCARD OF SINGLE-USE VECTOR REGISTER VALUES [patent_app_type] => utility [patent_app_number] => 18/737945 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737945
Opportunistic write-back discard of single-use vector register values Jun 6, 2024 Issued
Array ( [id] => 20537415 [patent_doc_number] => 12554492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Data processing systems and methods for controlling storage of input data values for use by an executing unit [patent_app_type] => utility [patent_app_number] => 18/734396 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 31655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734396
Data processing systems and methods for controlling storage of input data values for use by an executing unit Jun 4, 2024 Issued
Array ( [id] => 20273776 [patent_doc_number] => 12443558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width [patent_app_type] => utility [patent_app_number] => 18/670721 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 15715 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670721
Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width May 20, 2024 Issued
Array ( [id] => 19419942 [patent_doc_number] => 20240296065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/661804 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661804
STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS May 12, 2024 Pending
Array ( [id] => 20528973 [patent_doc_number] => 12547408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Multi-level PHT entry swaps based on first level miss and second level hit [patent_app_type] => utility [patent_app_number] => 18/654060 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654060 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654060
Multi-level PHT entry swaps based on first level miss and second level hit May 2, 2024 Issued
Array ( [id] => 20087215 [patent_doc_number] => 20250217151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => PROCESSOR PIPELINE FOR DATA TRANSFER OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/646992 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646992
Processor pipeline for interlocked data transfer operations with variable latency Apr 25, 2024 Issued
Array ( [id] => 19819023 [patent_doc_number] => 20250077230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => NEURAL NETWORK OPERATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/643336 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643336
NEURAL NETWORK OPERATION INSTRUCTIONS Apr 22, 2024 Pending
18/698684 PROCESSING SYSTEM OF THREAD BLOCK, METHOD AND RELATIVE DEVICE Apr 3, 2024 Pending
Array ( [id] => 19347311 [patent_doc_number] => 20240256274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/618648 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618648
Supporting 8-bit floating point format operands in a computing architecture Mar 26, 2024 Issued
Array ( [id] => 19747843 [patent_doc_number] => 20250036408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => COMPUTER SYSTEM CONFIGURED TO EXECUTE A COMPUTER PROGRAM [patent_app_type] => utility [patent_app_number] => 18/614049 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614049
Storing a duplicated return address and stack pointer in registers to prevent overflow attacks Mar 21, 2024 Issued
Array ( [id] => 19732874 [patent_doc_number] => 12210872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Neural processing device, processing element included therein and method for operating various formats of neural processing device [patent_app_type] => utility [patent_app_number] => 18/602924 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 24338 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602924
Neural processing device, processing element included therein and method for operating various formats of neural processing device Mar 11, 2024 Issued
Array ( [id] => 19334287 [patent_doc_number] => 20240248717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Atomic Operation Predictor to Predict Whether An Atomic Operation Will Complete Successfully [patent_app_type] => utility [patent_app_number] => 18/601640 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601640
Atomic operation predictor to predict whether an atomic operation will complete successfully Mar 10, 2024 Issued
Array ( [id] => 20181128 [patent_doc_number] => 20250265086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 18/442448 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442448
APPARATUS AND METHOD Feb 14, 2024 Pending
Array ( [id] => 19660536 [patent_doc_number] => 20240427601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => METHODS AND APPARATUS TO FACILITATE UNALIGNED BYTE STREAM OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/441796 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441796
METHODS AND APPARATUS TO FACILITATE UNALIGNED BYTE STREAM OPERATIONS Feb 13, 2024 Pending
Array ( [id] => 19362805 [patent_doc_number] => 20240264839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Macro-Op Fusion for Pipelined Architectures [patent_app_type] => utility [patent_app_number] => 18/428319 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428319
Macro-op fusion for pipelined architectures Jan 30, 2024 Issued
Array ( [id] => 20087259 [patent_doc_number] => 20250217195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => LOCAL LAUNCH IN WORKGROUP PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/401449 [patent_app_country] => US [patent_app_date] => 2023-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401449
LOCAL LAUNCH IN WORKGROUP PROCESSORS Dec 29, 2023 Pending
Array ( [id] => 19451370 [patent_doc_number] => 20240311500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => WORKFLOW EXECUTION STATE VARIABLES [patent_app_type] => utility [patent_app_number] => 18/400560 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400560
WORKFLOW EXECUTION STATE VARIABLES Dec 28, 2023 Pending
Array ( [id] => 20070641 [patent_doc_number] => 20250208863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => CONTROL OF INSTRUCTION ISSUE BASED ON ISSUE GROUPS [patent_app_type] => utility [patent_app_number] => 18/393825 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393825 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393825
Control of instruction issue based on issue groups Dec 21, 2023 Issued
Array ( [id] => 19114802 [patent_doc_number] => 20240126552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FUNCTION OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/393657 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393657
Processor-guided execution of offloaded instructions using fixed function operations Dec 20, 2023 Issued
Array ( [id] => 19544984 [patent_doc_number] => 20240362020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => APPARATUS AND METHODS RELATED TO MICROCODE INSTRUCTIONS INDICATING INSTRUCTION TYPES [patent_app_type] => utility [patent_app_number] => 18/532502 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/532502
Apparatus and methods related to microcode instructions indicating instruction types Dec 6, 2023 Issued
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