
Jacob Andrew Petranek
Examiner (ID: 11149, Phone: (571)272-5988 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183 |
| Total Applications | 1000 |
| Issued Applications | 752 |
| Pending Applications | 69 |
| Abandoned Applications | 205 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13961199
[patent_doc_number] => 20190056944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-21
[patent_title] => PREDICTING AND STORING A PREDICTED TARGET ADDRESS IN A PLURALITY OF SELECTED LOCATIONS
[patent_app_type] => utility
[patent_app_number] => 15/680809
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19264
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680809
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680809 | Predicting and storing a predicted target address in a plurality of selected locations | Aug 17, 2017 | Issued |
Array
(
[id] => 16045969
[patent_doc_number] => 10684856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-16
[patent_title] => Converting multiple instructions into a single combined instruction with an extension opcode
[patent_app_type] => utility
[patent_app_number] => 15/646219
[patent_app_country] => US
[patent_app_date] => 2017-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5690
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646219
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/646219 | Converting multiple instructions into a single combined instruction with an extension opcode | Jul 10, 2017 | Issued |
Array
(
[id] => 13611029
[patent_doc_number] => 20180357064
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => STREAM PROCESSOR WITH HIGH BANDWIDTH AND LOW POWER VECTOR REGISTER FILE
[patent_app_type] => utility
[patent_app_number] => 15/644045
[patent_app_country] => US
[patent_app_date] => 2017-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4884
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644045
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/644045 | Processor support for bypassing vector source operands | Jul 6, 2017 | Issued |
Array
(
[id] => 14735505
[patent_doc_number] => 10387152
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-20
[patent_title] => Selecting branch instruction execution paths based on previous branch path performance
[patent_app_type] => utility
[patent_app_number] => 15/642556
[patent_app_country] => US
[patent_app_date] => 2017-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3942
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642556
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/642556 | Selecting branch instruction execution paths based on previous branch path performance | Jul 5, 2017 | Issued |
Array
(
[id] => 15075385
[patent_doc_number] => 10467183
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-05
[patent_title] => Processors and methods for pipelined runtime services in a spatial array
[patent_app_type] => utility
[patent_app_number] => 15/640538
[patent_app_country] => US
[patent_app_date] => 2017-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 72
[patent_figures_cnt] => 92
[patent_no_of_words] => 51149
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640538
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640538 | Processors and methods for pipelined runtime services in a spatial array | Jun 30, 2017 | Issued |
Array
(
[id] => 13782529
[patent_doc_number] => 20190004803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => STATISTICAL CORRECTION FOR BRANCH PREDICTION MECHANISMS
[patent_app_type] => utility
[patent_app_number] => 15/640444
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5622
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640444
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640444 | STATISTICAL CORRECTION FOR BRANCH PREDICTION MECHANISMS | Jun 29, 2017 | Abandoned |
Array
(
[id] => 13782535
[patent_doc_number] => 20190004806
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => BRANCH PREDICTION FOR FIXED DIRECTION BRANCH INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 15/640441
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640441
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640441 | BRANCH PREDICTION FOR FIXED DIRECTION BRANCH INSTRUCTIONS | Jun 29, 2017 | Abandoned |
Array
(
[id] => 13782629
[patent_doc_number] => 20190004853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 15/636686
[patent_app_country] => US
[patent_app_date] => 2017-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636686
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/636686 | Streaming engine with short cut start instructions | Jun 28, 2017 | Issued |
Array
(
[id] => 13782551
[patent_doc_number] => 20190004814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => STREAM PROCESSOR WITH DECOUPLED CROSSBAR FOR CROSS LANE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 15/637629
[patent_app_country] => US
[patent_app_date] => 2017-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4282
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637629
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/637629 | Stream processor with decoupled crossbar for cross lane operations | Jun 28, 2017 | Issued |
Array
(
[id] => 17715251
[patent_doc_number] => 11379242
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Methods and apparatus for using load and store addresses to resolve memory dependencies
[patent_app_type] => utility
[patent_app_number] => 15/637637
[patent_app_country] => US
[patent_app_date] => 2017-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 8956
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637637
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/637637 | Methods and apparatus for using load and store addresses to resolve memory dependencies | Jun 28, 2017 | Issued |
Array
(
[id] => 12666016
[patent_doc_number] => 20180113838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-26
[patent_title] => SWITCHABLE TOPOLOGY MACHINE
[patent_app_type] => utility
[patent_app_number] => 15/637581
[patent_app_country] => US
[patent_app_date] => 2017-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12218
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637581
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/637581 | Switchable topology processor tile and computing machine | Jun 28, 2017 | Issued |
Array
(
[id] => 12495183
[patent_doc_number] => 09996346
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-12
[patent_title] => Multifunctional hexadecimal instruction form system and program product
[patent_app_type] => utility
[patent_app_number] => 15/635703
[patent_app_country] => US
[patent_app_date] => 2017-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 5331
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635703
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/635703 | Multifunctional hexadecimal instruction form system and program product | Jun 27, 2017 | Issued |
Array
(
[id] => 12053261
[patent_doc_number] => 20170329606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-16
[patent_title] => 'Systems, Apparatuses, and Methods for Performing Conflict Detection and Broadcasting Contents of a Register to Data Element Positions of Another Register'
[patent_app_type] => utility
[patent_app_number] => 15/608738
[patent_app_country] => US
[patent_app_date] => 2017-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11114
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608738
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/608738 | Systems, Apparatuses, and Methods for Performing Conflict Detection and Broadcasting Contents of a Register to Data Element Positions of Another Register | May 29, 2017 | Abandoned |
Array
(
[id] => 14149385
[patent_doc_number] => 10255073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-09
[patent_title] => Microcontroller with variable length move instructions using direct immediate addressing or indirect register offset addressing
[patent_app_type] => utility
[patent_app_number] => 15/592551
[patent_app_country] => US
[patent_app_date] => 2017-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 34
[patent_no_of_words] => 4856
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592551
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/592551 | Microcontroller with variable length move instructions using direct immediate addressing or indirect register offset addressing | May 10, 2017 | Issued |
Array
(
[id] => 17605867
[patent_doc_number] => 11334355
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-17
[patent_title] => Main processor prefetching operands for coprocessor operations
[patent_app_type] => utility
[patent_app_number] => 15/586937
[patent_app_country] => US
[patent_app_date] => 2017-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 13480
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586937
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/586937 | Main processor prefetching operands for coprocessor operations | May 3, 2017 | Issued |
Array
(
[id] => 16973045
[patent_doc_number] => 11069019
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Multi-threaded asynchronous frame processing
[patent_app_type] => utility
[patent_app_number] => 15/587341
[patent_app_country] => US
[patent_app_date] => 2017-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4438
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587341
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/587341 | Multi-threaded asynchronous frame processing | May 3, 2017 | Issued |
Array
(
[id] => 12032711
[patent_doc_number] => 20170322810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'HYPERVECTOR-BASED BRANCH PREDICTION'
[patent_app_type] => utility
[patent_app_number] => 15/587371
[patent_app_country] => US
[patent_app_date] => 2017-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4942
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587371
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/587371 | HYPERVECTOR-BASED BRANCH PREDICTION | May 3, 2017 | Abandoned |
Array
(
[id] => 16129851
[patent_doc_number] => 10698685
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations
[patent_app_type] => utility
[patent_app_number] => 15/586032
[patent_app_country] => US
[patent_app_date] => 2017-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 29
[patent_no_of_words] => 19089
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586032
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/586032 | Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations | May 2, 2017 | Issued |
Array
(
[id] => 13254865
[patent_doc_number] => 10140123
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-27
[patent_title] => SIMD processing lanes storing input pixel operand data in local register file for thread execution of image processing operations
[patent_app_type] => utility
[patent_app_number] => 15/483745
[patent_app_country] => US
[patent_app_date] => 2017-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4837
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483745
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/483745 | SIMD processing lanes storing input pixel operand data in local register file for thread execution of image processing operations | Apr 9, 2017 | Issued |
Array
(
[id] => 16535309
[patent_doc_number] => 10877910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Programmable event driven yield mechanism which may activate other threads
[patent_app_type] => utility
[patent_app_number] => 15/475680
[patent_app_country] => US
[patent_app_date] => 2017-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 7536
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475680
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/475680 | Programmable event driven yield mechanism which may activate other threads | Mar 30, 2017 | Issued |