Jacob Andrew Petranek

Array ( [id] => 19144624 [patent_doc_number] => 20240143541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => COMPUTE IN-MEMORY ARCHITECTURE FOR CONTINUOUS ON-CHIP LEARNING [patent_app_type] => utility [patent_app_number] => 18/384774 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19992749 [patent_doc_number] => 20250130971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => SUPERSCALAR FIELD PROGRAMMABLE GATE ARRAY (FPGA) VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/477195 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19917483 [patent_doc_number] => 12292852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Hierarchical networks on chip (NoC) for neural network accelerator [patent_app_type] => utility [patent_app_number] => 18/382938 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18382938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20922522 [patent_doc_number] => 12717583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Processor macro-operation fusion [patent_app_type] => utility [patent_app_number] => 18/491242 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18989712 [patent_doc_number] => 20240061681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => 3-LEVEL REAL-TIME CONCURRENT PRODUCTION OPERATION WORKGROUP SYSTEMS FOR FINE-GRAINED PROACTIVE CLOSED LOOP PROBLEM SOLVING OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/380868 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19925162 [patent_doc_number] => 12299447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Hardware verification of dynamically generated code [patent_app_type] => utility [patent_app_number] => 18/484582 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891908 [patent_doc_number] => 20250117220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => IN-CORE IMPLEMENTATION OF ADVANCED REDUCED INSTRUCTION SET COMPUTER MACHINE (ARM) SCALABLE MATRIX EXTENSIONS (SME) INSTRUCTION SET [patent_app_type] => utility [patent_app_number] => 18/481815 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925337 [patent_doc_number] => 20240028341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => GALOIS FIELD MULTIPLY REDUCTION AND PARALLEL HASH [patent_app_type] => utility [patent_app_number] => 18/375476 [patent_app_country] => US [patent_app_date] => 2023-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864759 [patent_doc_number] => 20250103545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => EXECUTION UNIT SHARING BETWEEN PROCESSING CORES IN A CLUSTER OF A SYSTEM-ON-CHIP (SOC) [patent_app_type] => utility [patent_app_number] => 18/473119 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20751859 [patent_doc_number] => 20260154087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-04 [patent_title] => PROCESSING SYSTEM OF THREAD BLOCK, METHOD AND RELATIVE DEVICE [patent_app_type] => utility [patent_app_number] => 18/698684 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18698684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18864169 [patent_doc_number] => 20230418605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => VECTOR LOAD AND DUPLICATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/243326 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19093027 [patent_doc_number] => 11954488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Neural processing device, processing element included therein and method for operating various formats of neural processing device [patent_app_type] => utility [patent_app_number] => 18/459241 [patent_app_country] => US [patent_app_date] => 2023-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 24318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19005846 [patent_doc_number] => 20240069917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => METHOD FOR EXECUTING A MACHINE CODE BY MEANS OF A COMPUTER [patent_app_type] => utility [patent_app_number] => 18/454173 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327923 [patent_doc_number] => 12045611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-23 [patent_title] => Reconfigurable neural network processing based on subgraph recognition [patent_app_type] => utility [patent_app_number] => 18/231024 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19596075 [patent_doc_number] => 12153923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-26 [patent_title] => Multi-card processor access framework [patent_app_type] => utility [patent_app_number] => 18/364971 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18941678 [patent_doc_number] => 20240036817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => SYSTEM-ON-A-CHIP INCLUDING SOFT FLOAT FUNCTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/362596 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18741740 [patent_doc_number] => 20230350721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => REDUCING DATA FORMAT CONVERSION OF AN ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/350197 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283790 [patent_doc_number] => 20240220266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR INTERMEDIARY REPRESENTATIONS OF WORKFLOWS FOR COMPUTATIONAL DEVICES [patent_app_type] => utility [patent_app_number] => 18/214522 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18904527 [patent_doc_number] => 20240020012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Memory Request Combination Indication [patent_app_type] => utility [patent_app_number] => 18/203901 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19015273 [patent_doc_number] => 11922208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-05 [patent_title] => Hybrid model for time series data processing [patent_app_type] => utility [patent_app_number] => 18/326255 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 15251 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326255 [rel_patent_id] =>[rel_patent_doc_number] =>)