Search

Jacob Andrew Petranek

Examiner (ID: 8886, Phone: (571)272-5988 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1019
Issued Applications
761
Pending Applications
76
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18584831 [patent_doc_number] => 20230267095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SYSTEMS AND METHODS FOR MULTI-BRANCH ROUTING FOR INTERCONNECTED CHIP NETWORKS [patent_app_type] => utility [patent_app_number] => 17/866345 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866345
Systems and methods for multi-branch routing for interconnected chip networks Jul 14, 2022 Issued
Array ( [id] => 17947823 [patent_doc_number] => 20220334842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => POWER EFFICIENT MULTI-BIT STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/859377 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/859377
Power efficient multi-bit storage system Jul 6, 2022 Issued
Array ( [id] => 19819262 [patent_doc_number] => 20250077469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => VOICE CHIP IMPLEMENTATION METHOD, VOICE CHIP, AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 18/025026 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025026
VOICE CHIP IMPLEMENTATION METHOD, VOICE CHIP, AND RELATED DEVICE Jun 27, 2022 Pending
Array ( [id] => 18007047 [patent_doc_number] => 20220365813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Apparatus, Device, Method, and Computer Program for Scheduling an Execution of Compute Kernels [patent_app_type] => utility [patent_app_number] => 17/809291 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809291
Apparatus, Device, Method, and Computer Program for Scheduling an Execution of Compute Kernels Jun 27, 2022 Pending
Array ( [id] => 18079620 [patent_doc_number] => 20220405232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => System on Chip Comprising a Connection Interface Between Master Devices and Slave Devices [patent_app_type] => utility [patent_app_number] => 17/835746 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835746
System on chip including a reconfigurable connection interface between master devices and slave devices Jun 7, 2022 Issued
Array ( [id] => 19228302 [patent_doc_number] => 12007938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width [patent_app_type] => utility [patent_app_number] => 17/827882 [patent_app_country] => US [patent_app_date] => 2022-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 22036 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827882
Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width May 29, 2022 Issued
Array ( [id] => 18007018 [patent_doc_number] => 20220365784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => MATRIX PROCESSING INSTRUCTION WITH OPTIONAL UP/DOWN SAMPLING OF MATRIX [patent_app_type] => utility [patent_app_number] => 17/824775 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824775
MATRIX PROCESSING INSTRUCTION WITH OPTIONAL UP/DOWN SAMPLING OF MATRIX May 24, 2022 Abandoned
Array ( [id] => 18856178 [patent_doc_number] => 11853762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-26 [patent_title] => Single instruction multiple data execution with variable size logical registers [patent_app_type] => utility [patent_app_number] => 17/749268 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4910 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749268
Single instruction multiple data execution with variable size logical registers May 19, 2022 Issued
Array ( [id] => 19719360 [patent_doc_number] => 12204899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Stochastic hyperdimensional arithmetic computing [patent_app_type] => utility [patent_app_number] => 17/744371 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 8180 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744371
Stochastic hyperdimensional arithmetic computing May 12, 2022 Issued
Array ( [id] => 18772911 [patent_doc_number] => 20230367738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => ASIC POWER CONTROL [patent_app_type] => utility [patent_app_number] => 17/741915 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741915
ASIC POWER CONTROL May 10, 2022 Pending
Array ( [id] => 17931832 [patent_doc_number] => 20220326957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => INDIRECT BRANCH PREDICTOR SECURITY PROTECTION [patent_app_type] => utility [patent_app_number] => 17/661696 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661696
Branch predictor storing encrypted information May 1, 2022 Issued
Array ( [id] => 18703383 [patent_doc_number] => 11789894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Acceleration system and dynamic configuration method thereof [patent_app_type] => utility [patent_app_number] => 17/720322 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4936 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720322
Acceleration system and dynamic configuration method thereof Apr 13, 2022 Issued
Array ( [id] => 20666424 [patent_doc_number] => 12608199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Instruction set architecture support for a load global pointer instruction [patent_app_type] => utility [patent_app_number] => 17/712126 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 50 [patent_no_of_words] => 29722 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712126
Instruction set architecture support for a load global pointer instruction Apr 1, 2022 Issued
Array ( [id] => 18677815 [patent_doc_number] => 20230315462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SYNCHRONOUS MICROTHREADING [patent_app_type] => utility [patent_app_number] => 17/712127 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712127
SYNCHRONOUS MICROTHREADING Apr 1, 2022 Pending
Array ( [id] => 19992750 [patent_doc_number] => 20250130972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => OVERLAYS FOR SOFTWARE AND HARDWARE VERIFICATION [patent_app_type] => utility [patent_app_number] => 18/553093 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18553093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/553093
OVERLAYS FOR SOFTWARE AND HARDWARE VERIFICATION Mar 29, 2022 Abandoned
Array ( [id] => 18539374 [patent_doc_number] => 20230244482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => TECHNIQUES, DEVICES, AND INSTRUCTION SET ARCHITECTURE FOR EFFICIENT MODULAR DIVISION AND INVERSION [patent_app_type] => utility [patent_app_number] => 17/707176 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707176
Techniques, devices, and instruction set architecture for efficient modular division and inversion Mar 28, 2022 Issued
Array ( [id] => 19740217 [patent_doc_number] => 12217052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Generating masks from decoded instructions to apply to fetched instructions for unmasking [patent_app_type] => utility [patent_app_number] => 17/656058 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8093 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656058
Generating masks from decoded instructions to apply to fetched instructions for unmasking Mar 22, 2022 Issued
Array ( [id] => 19925198 [patent_doc_number] => 12299484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Hardware and software co-designed system for efficient distributed control of execution on a compute accelerator [patent_app_type] => utility [patent_app_number] => 17/696137 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 3526 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696137
Hardware and software co-designed system for efficient distributed control of execution on a compute accelerator Mar 15, 2022 Issued
Array ( [id] => 20440288 [patent_doc_number] => 12511124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Static identifications in object-based memory access [patent_app_type] => utility [patent_app_number] => 17/693240 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693240
Static identifications in object-based memory access Mar 10, 2022 Issued
Array ( [id] => 17706790 [patent_doc_number] => 20220206796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/691615 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691615
MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR Mar 9, 2022 Abandoned
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