Search

Jacob D. Knutson

Examiner (ID: 10549, Phone: (571)270-5576 , Office: P/3611 )

Most Active Art Unit
3611
Art Unit(s)
3611, 4114
Total Applications
1184
Issued Applications
895
Pending Applications
94
Abandoned Applications
223

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17130639 [patent_doc_number] => 20210305408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => P-Metal Gate First Gate Replacement Process for Multigate Devices [patent_app_type] => utility [patent_app_number] => 16/834637 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834637 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834637
P-metal gate first gate replacement process for multigate devices Mar 29, 2020 Issued
Array ( [id] => 17863039 [patent_doc_number] => 11444201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Leakage current reduction in polysilicon-on-active-edge structures [patent_app_type] => utility [patent_app_number] => 16/831010 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6165 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831010
Leakage current reduction in polysilicon-on-active-edge structures Mar 25, 2020 Issued
Array ( [id] => 17115721 [patent_doc_number] => 20210296318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR DEVICE WITH IMPROVED DEVICE PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/823792 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823792 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823792
Semiconductor device with improved device performance Mar 18, 2020 Issued
Array ( [id] => 16677732 [patent_doc_number] => 20210066498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => MINIMIZATION OF SILICON GERMANIUM FACETS IN PLANAR METAL OXIDE SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/821690 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821690 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821690
Minimization of silicon germanium facets in planar metal oxide semiconductor structures Mar 16, 2020 Issued
Array ( [id] => 16163283 [patent_doc_number] => 20200219874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Fin Cut to Prevent Replacement Gate Collapse on STI [patent_app_type] => utility [patent_app_number] => 16/807731 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807731
Fin cut to prevent replacement gate collapse on STI Mar 2, 2020 Issued
Array ( [id] => 17224849 [patent_doc_number] => 11177359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 16/807614 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 9913 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807614
Semiconductor device and manufacturing method of semiconductor device Mar 2, 2020 Issued
Array ( [id] => 16677733 [patent_doc_number] => 20210066499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/805958 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805958
Semiconductor device and method Mar 1, 2020 Issued
Array ( [id] => 17284111 [patent_doc_number] => 11201153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Stacked field effect transistor with wrap-around contacts [patent_app_type] => utility [patent_app_number] => 16/801904 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10355 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801904
Stacked field effect transistor with wrap-around contacts Feb 25, 2020 Issued
Array ( [id] => 17056073 [patent_doc_number] => 20210265507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/799215 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799215
Semiconductor structure and manufacturing method for the semiconductor structure Feb 23, 2020 Issued
Array ( [id] => 17326552 [patent_doc_number] => 11217577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Controlled resistance integrated snubber for power switching device [patent_app_type] => utility [patent_app_number] => 16/789810 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6499 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789810 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789810
Controlled resistance integrated snubber for power switching device Feb 12, 2020 Issued
Array ( [id] => 16099163 [patent_doc_number] => 20200203568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => LIGHT EMITTING DIODE HAVING SIDE REFLECTION LAYER [patent_app_type] => utility [patent_app_number] => 16/789215 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789215
Light emitting diode having side reflection layer Feb 11, 2020 Issued
Array ( [id] => 17025480 [patent_doc_number] => 20210249352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => SEMICONDUCTOR DEVICE WITH METAL STRUCTURE UNDER AN ACTIVE LAYER [patent_app_type] => utility [patent_app_number] => 16/784256 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784256
Semiconductor device with metal structure under an active layer Feb 6, 2020 Issued
Array ( [id] => 17590863 [patent_doc_number] => 11329140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/745796 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 66 [patent_no_of_words] => 11272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745796 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745796
Semiconductor device and method of manufacture Jan 16, 2020 Issued
Array ( [id] => 17254117 [patent_doc_number] => 11189615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/739357 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 41 [patent_no_of_words] => 10835 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/739357
Semiconductor devices Jan 9, 2020 Issued
Array ( [id] => 15873483 [patent_doc_number] => 20200144145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => WAFER-LEVEL CHIP-SCALE PACKAGE INCLUDING POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/734688 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734688
Wafer-level chip-scale package including power semiconductor and manufacturing method thereof Jan 5, 2020 Issued
Array ( [id] => 17971311 [patent_doc_number] => 11488859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 16/728145 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 13642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728145 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728145
Semiconductor device and method Dec 26, 2019 Issued
Array ( [id] => 16936590 [patent_doc_number] => 20210202479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTERNATE ETCH SELECTIVE MATERIAL [patent_app_type] => utility [patent_app_number] => 16/727355 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727355 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727355
Gate-all-around integrated circuit structures fabricated using alternate etch selective material Dec 25, 2019 Issued
Array ( [id] => 17668490 [patent_doc_number] => 11362195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Semiconductor device and a method for forming a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/723742 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723742
Semiconductor device and a method for forming a semiconductor device Dec 19, 2019 Issued
Array ( [id] => 15775983 [patent_doc_number] => 20200119009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/716384 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716384
Semiconductor device and method of manufacturing the same Dec 15, 2019 Issued
Array ( [id] => 16905085 [patent_doc_number] => 20210184001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => NANORIBBON THICK GATE DEVICES WITH DIFFERENTIAL RIBBON SPACING AND WIDTH FOR SOC APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/713684 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713684
Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications Dec 12, 2019 Issued
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