Search

Jacob James Cigna

Examiner (ID: 13885, Phone: (571)270-5262 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726, 4176, RD00
Total Applications
967
Issued Applications
579
Pending Applications
85
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10894810 [patent_doc_number] => 08918441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'NAF conversion apparatus' [patent_app_type] => utility [patent_app_number] => 13/183625 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4198 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13183625 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/183625
NAF conversion apparatus Jul 14, 2011 Issued
Array ( [id] => 8613620 [patent_doc_number] => 20130018932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'SYSTEM AND METHOD FOR LONG RANGE AND SHORT RANGE DATA COMPRESSION' [patent_app_type] => utility [patent_app_number] => 13/180969 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13180969 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180969
SYSTEM AND METHOD FOR LONG RANGE AND SHORT RANGE DATA COMPRESSION Jul 11, 2011 Abandoned
Array ( [id] => 9651883 [patent_doc_number] => 08805917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Parallel redundant decimal fused-multiply-add circuit' [patent_app_type] => utility [patent_app_number] => 13/177491 [patent_app_country] => US [patent_app_date] => 2011-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13177491 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177491
Parallel redundant decimal fused-multiply-add circuit Jul 5, 2011 Issued
Array ( [id] => 7721847 [patent_doc_number] => 20120011182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'DECIMAL FLOATING-POINT SQUARE-ROOT UNIT USING NEWTON-RAPHSON ITERATIONS' [patent_app_type] => utility [patent_app_number] => 13/177488 [patent_app_country] => US [patent_app_date] => 2011-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011182.pdf [firstpage_image] =>[orig_patent_app_number] => 13177488 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177488
Decimal floating-point square-root unit using Newton-Raphson iterations Jul 5, 2011 Issued
Array ( [id] => 7735462 [patent_doc_number] => 20120016919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'EXTENDED-WIDTH SHIFTER FOR ARITHMETIC LOGIC UNIT' [patent_app_type] => utility [patent_app_number] => 13/175938 [patent_app_country] => US [patent_app_date] => 2011-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20120016919.pdf [firstpage_image] =>[orig_patent_app_number] => 13175938 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175938
Extended-width shifter for arithmetic logic unit Jul 3, 2011 Issued
Array ( [id] => 8337102 [patent_doc_number] => 20120203811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'METHOD AND APPARATUS FOR CALCULATING THE NUMBER OF LEADING ZERO BITS OF A BINARY OPERATION' [patent_app_type] => utility [patent_app_number] => 13/171536 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171536 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/171536
Method and apparatus for calculating the number of leading zero bits of a binary operation Jun 28, 2011 Issued
Array ( [id] => 9592549 [patent_doc_number] => 08782112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Methods and systems for optimal zero-forcing and MMSE frequency domain equalizers for complex and VSB signals' [patent_app_type] => utility [patent_app_number] => 13/171300 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 12762 [patent_no_of_claims] => 127 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171300 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/171300
Methods and systems for optimal zero-forcing and MMSE frequency domain equalizers for complex and VSB signals Jun 27, 2011 Issued
Array ( [id] => 7503570 [patent_doc_number] => 20110264724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Apparatus, Methods, and HDL Code for Determining the Coefficients of a Function With Decreased Latency' [patent_app_type] => utility [patent_app_number] => 13/169637 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21077 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20110264724.pdf [firstpage_image] =>[orig_patent_app_number] => 13169637 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/169637
Apparatus, Methods, and HDL Code for Determining the Coefficients of a Function With Decreased Latency Jun 26, 2011 Abandoned
Array ( [id] => 9404501 [patent_doc_number] => 08694565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Language integrated query over vector spaces' [patent_app_type] => utility [patent_app_number] => 13/161933 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13161933 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161933
Language integrated query over vector spaces Jun 15, 2011 Issued
Array ( [id] => 9973968 [patent_doc_number] => 09021003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Processor and operating method' [patent_app_type] => utility [patent_app_number] => 13/805519 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9318 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13805519 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/805519
Processor and operating method Jun 15, 2011 Issued
Array ( [id] => 9592547 [patent_doc_number] => 08782111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Digital filter' [patent_app_type] => utility [patent_app_number] => 13/155869 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155869
Digital filter Jun 7, 2011 Issued
Array ( [id] => 9527267 [patent_doc_number] => 08751556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Processor for large graph algorithm computations and matrix operations' [patent_app_type] => utility [patent_app_number] => 13/153490 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15740 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153490
Processor for large graph algorithm computations and matrix operations Jun 5, 2011 Issued
Array ( [id] => 9651880 [patent_doc_number] => 08805913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Method of evaluating a function and associated device' [patent_app_type] => utility [patent_app_number] => 13/116391 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116391
Method of evaluating a function and associated device May 25, 2011 Issued
Array ( [id] => 9611366 [patent_doc_number] => 08788556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Matrix computation framework' [patent_app_type] => utility [patent_app_number] => 13/105915 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13105915 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105915
Matrix computation framework May 11, 2011 Issued
Array ( [id] => 9347883 [patent_doc_number] => 08667045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'Generalized parallel counter structures in logic devices' [patent_app_type] => utility [patent_app_number] => 13/105133 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3579 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13105133 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105133
Generalized parallel counter structures in logic devices May 10, 2011 Issued
Array ( [id] => 9532380 [patent_doc_number] => 08756265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-17 [patent_title] => 'Audio filter bank design' [patent_app_type] => utility [patent_app_number] => 13/097633 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7048 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/097633
Audio filter bank design Apr 28, 2011 Issued
Array ( [id] => 7735460 [patent_doc_number] => 20120016918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'Method for Compressing Information' [patent_app_type] => utility [patent_app_number] => 13/092805 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3337 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20120016918.pdf [firstpage_image] =>[orig_patent_app_number] => 13092805 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092805
Method for Compressing Information Apr 21, 2011 Abandoned
Array ( [id] => 9555369 [patent_doc_number] => 08762439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'System and method for random number generation using asynchronous boundaries and phase locked loops' [patent_app_type] => utility [patent_app_number] => 13/086996 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5287 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13086996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/086996
System and method for random number generation using asynchronous boundaries and phase locked loops Apr 13, 2011 Issued
Array ( [id] => 9430710 [patent_doc_number] => 08706795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'SIMD integer addition including mathematical operation on masks' [patent_app_type] => utility [patent_app_number] => 13/391263 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4070 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/391263
SIMD integer addition including mathematical operation on masks Mar 29, 2011 Issued
Array ( [id] => 7695123 [patent_doc_number] => 20110231467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'MONTGOMERY MULTIPLIER HAVING EFFICIENT HARDWARE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/052524 [patent_app_country] => US [patent_app_date] => 2011-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20110231467.pdf [firstpage_image] =>[orig_patent_app_number] => 13052524 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/052524
Montgomery multiplier having efficient hardware structure Mar 20, 2011 Issued
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