Search

Jacqueline V. Howard

Examiner (ID: 13731)

Most Active Art Unit
1108
Art Unit(s)
1111, 1106, 1721, 1101, 1109, 1505, 1764, 1107, 2899, 1108
Total Applications
2212
Issued Applications
1851
Pending Applications
77
Abandoned Applications
284

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3789521 [patent_doc_number] => 05808960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Circuit and method for tracking the start of a write to a memory cell' [patent_app_type] => 1 [patent_app_number] => 8/858295 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 20322 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808960.pdf [firstpage_image] =>[orig_patent_app_number] => 858295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858295
Circuit and method for tracking the start of a write to a memory cell May 18, 1997 Issued
Array ( [id] => 3845783 [patent_doc_number] => 05815454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Semiconductor memory device having power line arranged in a meshed shape' [patent_app_type] => 1 [patent_app_number] => 8/831788 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 12729 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815454.pdf [firstpage_image] =>[orig_patent_app_number] => 831788 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831788
Semiconductor memory device having power line arranged in a meshed shape Apr 8, 1997 Issued
Array ( [id] => 3898869 [patent_doc_number] => 05724293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Semiconductor memory device having power line arranged in a meshed shape' [patent_app_type] => 1 [patent_app_number] => 8/816102 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 12729 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724293.pdf [firstpage_image] =>[orig_patent_app_number] => 816102 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816102
Semiconductor memory device having power line arranged in a meshed shape Mar 13, 1997 Issued
Array ( [id] => 3913098 [patent_doc_number] => 05751649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'High speed memory output circuitry and methods for implementing same' [patent_app_type] => 1 [patent_app_number] => 8/806335 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6370 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751649.pdf [firstpage_image] =>[orig_patent_app_number] => 806335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806335
High speed memory output circuitry and methods for implementing same Feb 25, 1997 Issued
Array ( [id] => 3780689 [patent_doc_number] => 05734603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method and circuit for reducing cell plate noise' [patent_app_type] => 1 [patent_app_number] => 8/797840 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3103 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734603.pdf [firstpage_image] =>[orig_patent_app_number] => 797840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797840
Method and circuit for reducing cell plate noise Feb 9, 1997 Issued
Array ( [id] => 3844728 [patent_doc_number] => 05761141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Semiconductor memory device and test method therefor' [patent_app_type] => 1 [patent_app_number] => 8/782038 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4944 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761141.pdf [firstpage_image] =>[orig_patent_app_number] => 782038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782038
Semiconductor memory device and test method therefor Jan 12, 1997 Issued
Array ( [id] => 3888956 [patent_doc_number] => 05764592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'External write pulse control method and structure' [patent_app_type] => 1 [patent_app_number] => 8/771642 [patent_app_country] => US [patent_app_date] => 1996-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3057 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764592.pdf [firstpage_image] =>[orig_patent_app_number] => 771642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/771642
External write pulse control method and structure Dec 20, 1996 Issued
Array ( [id] => 4067319 [patent_doc_number] => 05864507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Dual level wordline clamp for reduced memory cell current' [patent_app_type] => 1 [patent_app_number] => 8/769241 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864507.pdf [firstpage_image] =>[orig_patent_app_number] => 769241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769241
Dual level wordline clamp for reduced memory cell current Dec 17, 1996 Issued
Array ( [id] => 3780755 [patent_doc_number] => 05734606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Multi-piece cell and a MRAM array including the cell' [patent_app_type] => 1 [patent_app_number] => 8/767240 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734606.pdf [firstpage_image] =>[orig_patent_app_number] => 767240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767240
Multi-piece cell and a MRAM array including the cell Dec 12, 1996 Issued
Array ( [id] => 3632932 [patent_doc_number] => 05686730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Dimm pair with data memory and state memory' [patent_app_type] => 1 [patent_app_number] => 8/747976 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9387 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686730.pdf [firstpage_image] =>[orig_patent_app_number] => 747976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747976
Dimm pair with data memory and state memory Nov 11, 1996 Issued
Array ( [id] => 3830380 [patent_doc_number] => 05790447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'High-memory capacity DIMM with data and state memory' [patent_app_type] => 1 [patent_app_number] => 8/747975 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9363 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790447.pdf [firstpage_image] =>[orig_patent_app_number] => 747975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747975
High-memory capacity DIMM with data and state memory Nov 11, 1996 Issued
Array ( [id] => 3866597 [patent_doc_number] => 05768173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Memory modules, circuit substrates and methods of fabrication therefor using partially defective memory devices' [patent_app_type] => 1 [patent_app_number] => 8/744440 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3249 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768173.pdf [firstpage_image] =>[orig_patent_app_number] => 744440 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744440
Memory modules, circuit substrates and methods of fabrication therefor using partially defective memory devices Nov 7, 1996 Issued
Array ( [id] => 3772476 [patent_doc_number] => 05742552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Timing control for clocked sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 8/740636 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5364 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742552.pdf [firstpage_image] =>[orig_patent_app_number] => 740636 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/740636
Timing control for clocked sense amplifiers Oct 30, 1996 Issued
Array ( [id] => 3892589 [patent_doc_number] => 05748549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/735835 [patent_app_country] => US [patent_app_date] => 1996-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 2872 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748549.pdf [firstpage_image] =>[orig_patent_app_number] => 735835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735835
Semiconductor memory device Oct 22, 1996 Issued
Array ( [id] => 3853787 [patent_doc_number] => 05745413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Electrically programmable nonvolatile semiconductor memory device with NAND cell structure' [patent_app_type] => 1 [patent_app_number] => 8/731914 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 13551 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745413.pdf [firstpage_image] =>[orig_patent_app_number] => 731914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731914
Electrically programmable nonvolatile semiconductor memory device with NAND cell structure Oct 21, 1996 Issued
Array ( [id] => 3804672 [patent_doc_number] => 05726949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Semiconductor memory device having a redundant configuration' [patent_app_type] => 1 [patent_app_number] => 8/735141 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6298 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726949.pdf [firstpage_image] =>[orig_patent_app_number] => 735141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735141
Semiconductor memory device having a redundant configuration Oct 21, 1996 Issued
Array ( [id] => 3752069 [patent_doc_number] => 05787038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/730872 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1657 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787038.pdf [firstpage_image] =>[orig_patent_app_number] => 730872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730872
Flash memory device Oct 17, 1996 Issued
Array ( [id] => 3858456 [patent_doc_number] => 05719817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Memory array using selective device activation' [patent_app_type] => 1 [patent_app_number] => 8/727836 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719817.pdf [firstpage_image] =>[orig_patent_app_number] => 727836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727836
Memory array using selective device activation Oct 14, 1996 Issued
Array ( [id] => 3844618 [patent_doc_number] => 05761132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Integrated circuit memory devices with latch-free page buffers therein for preventing read failures' [patent_app_type] => 1 [patent_app_number] => 8/725641 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3235 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761132.pdf [firstpage_image] =>[orig_patent_app_number] => 725641 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725641
Integrated circuit memory devices with latch-free page buffers therein for preventing read failures Oct 14, 1996 Issued
Array ( [id] => 3753174 [patent_doc_number] => 05754469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Page mode floating gate memory device storing multiple bits per cell' [patent_app_type] => 1 [patent_app_number] => 8/718335 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12966 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754469.pdf [firstpage_image] =>[orig_patent_app_number] => 718335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718335
Page mode floating gate memory device storing multiple bits per cell Sep 30, 1996 Issued
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