
Jacqueline V. Howard
Examiner (ID: 13731)
| Most Active Art Unit | 1108 |
| Art Unit(s) | 1111, 1106, 1721, 1101, 1109, 1505, 1764, 1107, 2899, 1108 |
| Total Applications | 2212 |
| Issued Applications | 1851 |
| Pending Applications | 77 |
| Abandoned Applications | 284 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2715816
[patent_doc_number] => 05068829
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-26
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/570525
[patent_app_country] => US
[patent_app_date] => 1990-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 10014
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/068/05068829.pdf
[firstpage_image] =>[orig_patent_app_number] => 570525
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/570525 | Semiconductor memory device | Aug 20, 1990 | Issued |
Array
(
[id] => 2718614
[patent_doc_number] => 05056064
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-08
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/568734
[patent_app_country] => US
[patent_app_date] => 1990-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 47
[patent_no_of_words] => 19170
[patent_no_of_claims] => 41
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[patent_words_short_claim] => 169
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/056/05056064.pdf
[firstpage_image] =>[orig_patent_app_number] => 568734
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/568734 | Semiconductor integrated circuit | Aug 16, 1990 | Issued |
Array
(
[id] => 2861887
[patent_doc_number] => 05134587
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-28
[patent_title] => 'Semiconductor memory with automatic test mode exit on chip enable'
[patent_app_type] => 1
[patent_app_number] => 7/570149
[patent_app_country] => US
[patent_app_date] => 1990-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 23675
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/134/05134587.pdf
[firstpage_image] =>[orig_patent_app_number] => 570149
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/570149 | Semiconductor memory with automatic test mode exit on chip enable | Aug 16, 1990 | Issued |
Array
(
[id] => 2861869
[patent_doc_number] => 05134586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-28
[patent_title] => 'Semiconductor memory with chip enable control from output enable during test mode'
[patent_app_type] => 1
[patent_app_number] => 7/569002
[patent_app_country] => US
[patent_app_date] => 1990-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 23463
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/134/05134586.pdf
[firstpage_image] =>[orig_patent_app_number] => 569002
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/569002 | Semiconductor memory with chip enable control from output enable during test mode | Aug 16, 1990 | Issued |
Array
(
[id] => 2833979
[patent_doc_number] => 05170376
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-08
[patent_title] => 'Asynchronous timing circuit for a 2-coordinate memory'
[patent_app_type] => 1
[patent_app_number] => 7/573205
[patent_app_country] => US
[patent_app_date] => 1990-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3965
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/170/05170376.pdf
[firstpage_image] =>[orig_patent_app_number] => 573205
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/573205 | Asynchronous timing circuit for a 2-coordinate memory | Aug 12, 1990 | Issued |
Array
(
[id] => 2904506
[patent_doc_number] => 05270973
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-14
[patent_title] => 'Video random access memory having a split register and a multiplexer'
[patent_app_type] => 1
[patent_app_number] => 7/563471
[patent_app_country] => US
[patent_app_date] => 1990-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 7778
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/270/05270973.pdf
[firstpage_image] =>[orig_patent_app_number] => 563471
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/563471 | Video random access memory having a split register and a multiplexer | Aug 5, 1990 | Issued |
Array
(
[id] => 2864969
[patent_doc_number] => 05113373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-12
[patent_title] => 'Power control circuit'
[patent_app_type] => 1
[patent_app_number] => 7/563061
[patent_app_country] => US
[patent_app_date] => 1990-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3553
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/113/05113373.pdf
[firstpage_image] =>[orig_patent_app_number] => 563061
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/563061 | Power control circuit | Aug 5, 1990 | Issued |
Array
(
[id] => 2869897
[patent_doc_number] => 05083294
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-21
[patent_title] => 'Semiconductor memory device having a redundancy'
[patent_app_type] => 1
[patent_app_number] => 7/562512
[patent_app_country] => US
[patent_app_date] => 1990-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6288
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 1001
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/083/05083294.pdf
[firstpage_image] =>[orig_patent_app_number] => 562512
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/562512 | Semiconductor memory device having a redundancy | Aug 2, 1990 | Issued |
Array
(
[id] => 2692047
[patent_doc_number] => 05046044
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'SEU hardened memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/563722
[patent_app_country] => US
[patent_app_date] => 1990-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 3592
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/046/05046044.pdf
[firstpage_image] =>[orig_patent_app_number] => 563722
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/563722 | SEU hardened memory cell | Jul 31, 1990 | Issued |
| 07/560542 | VOLTAGE LEVEL DETECTION CIRCUIT | Jul 30, 1990 | Abandoned |
Array
(
[id] => 2985339
[patent_doc_number] => 05208776
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-04
[patent_title] => 'Pulse generation circuit'
[patent_app_type] => 1
[patent_app_number] => 7/560962
[patent_app_country] => US
[patent_app_date] => 1990-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 191
[patent_figures_cnt] => 236
[patent_no_of_words] => 111795
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/208/05208776.pdf
[firstpage_image] =>[orig_patent_app_number] => 560962
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/560962 | Pulse generation circuit | Jul 30, 1990 | Issued |
Array
(
[id] => 2949651
[patent_doc_number] => 05191555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-02
[patent_title] => 'CMOS single input buffer for multiplexed inputs'
[patent_app_type] => 1
[patent_app_number] => 7/560541
[patent_app_country] => US
[patent_app_date] => 1990-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 191
[patent_figures_cnt] => 236
[patent_no_of_words] => 112442
[patent_no_of_claims] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/191/05191555.pdf
[firstpage_image] =>[orig_patent_app_number] => 560541
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/560541 | CMOS single input buffer for multiplexed inputs | Jul 30, 1990 | Issued |
Array
(
[id] => 2944338
[patent_doc_number] => 05220534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'Substrate bias generator system'
[patent_app_type] => 1
[patent_app_number] => 7/560662
[patent_app_country] => US
[patent_app_date] => 1990-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 191
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/220/05220534.pdf
[firstpage_image] =>[orig_patent_app_number] => 560662
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/560662 | Substrate bias generator system | Jul 30, 1990 | Issued |
Array
(
[id] => 2864933
[patent_doc_number] => 05113371
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-12
[patent_title] => 'Semiconductor memory apparatus with a spare memory cell array'
[patent_app_type] => 1
[patent_app_number] => 7/557841
[patent_app_country] => US
[patent_app_date] => 1990-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3763
[patent_no_of_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/113/05113371.pdf
[firstpage_image] =>[orig_patent_app_number] => 557841
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/557841 | Semiconductor memory apparatus with a spare memory cell array | Jul 25, 1990 | Issued |
Array
(
[id] => 2881821
[patent_doc_number] => 05091888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-25
[patent_title] => 'Semiconductor memory device'
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[patent_app_number] => 7/552972
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[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/091/05091888.pdf
[firstpage_image] =>[orig_patent_app_number] => 552972
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/552972 | Semiconductor memory device | Jul 11, 1990 | Issued |
Array
(
[id] => 2955847
[patent_doc_number] => 05181188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-19
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/549293
[patent_app_country] => US
[patent_app_date] => 1990-07-06
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[pdf_file] => patents/05/181/05181188.pdf
[firstpage_image] =>[orig_patent_app_number] => 549293
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/549293 | Semiconductor memory device | Jul 5, 1990 | Issued |
Array
(
[id] => 2823670
[patent_doc_number] => 05079744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Test apparatus for static-type semiconductor memory devices'
[patent_app_type] => 1
[patent_app_number] => 7/547251
[patent_app_country] => US
[patent_app_date] => 1990-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/079/05079744.pdf
[firstpage_image] =>[orig_patent_app_number] => 547251
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/547251 | Test apparatus for static-type semiconductor memory devices | Jul 2, 1990 | Issued |
| 07/545790 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE | Jun 28, 1990 | Abandoned |
| 07/546251 | CIRCUIT CONFIGURATION FOR IDENTIFICATION OF INTEGRATED SEMICONDUCTOR CIRCUITRIES | Jun 28, 1990 | Abandoned |
Array
(
[id] => 2830680
[patent_doc_number] => 05173873
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-22
[patent_title] => 'High speed magneto-resistive random access memory'
[patent_app_type] => 1
[patent_app_number] => 7/545019
[patent_app_country] => US
[patent_app_date] => 1990-06-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/173/05173873.pdf
[firstpage_image] =>[orig_patent_app_number] => 545019
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/545019 | High speed magneto-resistive random access memory | Jun 27, 1990 | Issued |