| Application number | Title of the application | Filing Date | Status |
|---|
| 07/546071 | RANDOM ACCESS CACHE MEMORY | Jun 26, 1990 | Abandoned |
| 07/544071 | MEMORY CELL WITH KNOWN STATE ON POWER-UP | Jun 25, 1990 | Abandoned |
Array
(
[id] => 3067699
[patent_doc_number] => RE034535
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-08
[patent_title] => 'Floating gate memory with improved dielectric'
[patent_app_type] => 2
[patent_app_number] => 7/541435
[patent_app_country] => US
[patent_app_date] => 1990-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 5084
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/034/RE034535.pdf
[firstpage_image] =>[orig_patent_app_number] => 541435
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/541435 | Floating gate memory with improved dielectric | Jun 21, 1990 | Issued |
Array
(
[id] => 2715796
[patent_doc_number] => 05068828
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-26
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/540480
[patent_app_country] => US
[patent_app_date] => 1990-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7865
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 399
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/068/05068828.pdf
[firstpage_image] =>[orig_patent_app_number] => 540480
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/540480 | Semiconductor memory device | Jun 18, 1990 | Issued |
Array
(
[id] => 2857763
[patent_doc_number] => 05107460
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-21
[patent_title] => 'Spatial optical modulator'
[patent_app_type] => 1
[patent_app_number] => 7/535728
[patent_app_country] => US
[patent_app_date] => 1990-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 10035
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/107/05107460.pdf
[firstpage_image] =>[orig_patent_app_number] => 535728
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/535728 | Spatial optical modulator | Jun 10, 1990 | Issued |
Array
(
[id] => 2776315
[patent_doc_number] => 05036485
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Bloch-line memory device capable of stably generating a magnetic domain'
[patent_app_type] => 1
[patent_app_number] => 7/533511
[patent_app_country] => US
[patent_app_date] => 1990-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3978
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 454
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/036/05036485.pdf
[firstpage_image] =>[orig_patent_app_number] => 533511
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/533511 | Bloch-line memory device capable of stably generating a magnetic domain | Jun 4, 1990 | Issued |
Array
(
[id] => 2766790
[patent_doc_number] => 05043947
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-27
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/530304
[patent_app_country] => US
[patent_app_date] => 1990-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 10833
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/043/05043947.pdf
[firstpage_image] =>[orig_patent_app_number] => 530304
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/530304 | Semiconductor memory device | May 29, 1990 | Issued |
Array
(
[id] => 2854100
[patent_doc_number] => 05138580
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Method for the erasure of memory cells, device designed to implement it, and use of said method in a device with non-supplied memory'
[patent_app_type] => 1
[patent_app_number] => 7/530230
[patent_app_country] => US
[patent_app_date] => 1990-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2384
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138580.pdf
[firstpage_image] =>[orig_patent_app_number] => 530230
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/530230 | Method for the erasure of memory cells, device designed to implement it, and use of said method in a device with non-supplied memory | May 29, 1990 | Issued |
Array
(
[id] => 2847762
[patent_doc_number] => 05161123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-03
[patent_title] => 'Semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 7/527821
[patent_app_country] => US
[patent_app_date] => 1990-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 2755
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/161/05161123.pdf
[firstpage_image] =>[orig_patent_app_number] => 527821
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/527821 | Semiconductor memory | May 23, 1990 | Issued |
Array
(
[id] => 2797948
[patent_doc_number] => 05101380
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/527798
[patent_app_country] => US
[patent_app_date] => 1990-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 7095
[patent_no_of_claims] => 95
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/101/05101380.pdf
[firstpage_image] =>[orig_patent_app_number] => 527798
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/527798 | Semiconductor memory device | May 22, 1990 | Issued |
| 07/523820 | APPARATUS FOR SELECTING NUMBER OF WAIT STATED IN A BURST EPROM ARCHITECTURE | May 14, 1990 | Abandoned |
Array
(
[id] => 2880673
[patent_doc_number] => 05163024
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Video display system using memory with parallel and serial access employing serial shift registers selected by column address'
[patent_app_type] => 1
[patent_app_number] => 7/520986
[patent_app_country] => US
[patent_app_date] => 1990-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 9448
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/163/05163024.pdf
[firstpage_image] =>[orig_patent_app_number] => 520986
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/520986 | Video display system using memory with parallel and serial access employing serial shift registers selected by column address | May 8, 1990 | Issued |
Array
(
[id] => 2718991
[patent_doc_number] => 05042010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-20
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/520620
[patent_app_country] => US
[patent_app_date] => 1990-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 11409
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/042/05042010.pdf
[firstpage_image] =>[orig_patent_app_number] => 520620
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/520620 | Semiconductor integrated circuit | May 7, 1990 | Issued |
| 07/515323 | METHOD FOR TRANSFERRING A BLOCH LINE | Apr 29, 1990 | Abandoned |
Array
(
[id] => 2783775
[patent_doc_number] => 05075890
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-24
[patent_title] => 'Electrically erasable programmable read-only memory with NAND cell'
[patent_app_type] => 1
[patent_app_number] => 7/516311
[patent_app_country] => US
[patent_app_date] => 1990-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5815
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/075/05075890.pdf
[firstpage_image] =>[orig_patent_app_number] => 516311
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/516311 | Electrically erasable programmable read-only memory with NAND cell | Apr 29, 1990 | Issued |
Array
(
[id] => 2858742
[patent_doc_number] => 05111433
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-05
[patent_title] => 'Semiconductor memory device with inhibiting test mode cancellation and operating method thereof'
[patent_app_type] => 1
[patent_app_number] => 7/515501
[patent_app_country] => US
[patent_app_date] => 1990-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 6652
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/111/05111433.pdf
[firstpage_image] =>[orig_patent_app_number] => 515501
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/515501 | Semiconductor memory device with inhibiting test mode cancellation and operating method thereof | Apr 26, 1990 | Issued |
Array
(
[id] => 2964083
[patent_doc_number] => 05231602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-27
[patent_title] => 'Apparatus and method for improving the endurance of floating gate devices'
[patent_app_type] => 1
[patent_app_number] => 7/514520
[patent_app_country] => US
[patent_app_date] => 1990-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3009
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/231/05231602.pdf
[firstpage_image] =>[orig_patent_app_number] => 514520
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/514520 | Apparatus and method for improving the endurance of floating gate devices | Apr 24, 1990 | Issued |
Array
(
[id] => 2889152
[patent_doc_number] => 05119337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-02
[patent_title] => 'Semiconductor memory device having burn-in test function'
[patent_app_type] => 1
[patent_app_number] => 7/509212
[patent_app_country] => US
[patent_app_date] => 1990-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3079
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/119/05119337.pdf
[firstpage_image] =>[orig_patent_app_number] => 509212
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/509212 | Semiconductor memory device having burn-in test function | Apr 15, 1990 | Issued |
Array
(
[id] => 2785815
[patent_doc_number] => 05132935
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-21
[patent_title] => 'Erasure of eeprom memory arrays to prevent over-erased cells'
[patent_app_type] => 1
[patent_app_number] => 7/509532
[patent_app_country] => US
[patent_app_date] => 1990-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5586
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/132/05132935.pdf
[firstpage_image] =>[orig_patent_app_number] => 509532
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/509532 | Erasure of eeprom memory arrays to prevent over-erased cells | Apr 15, 1990 | Issued |
Array
(
[id] => 2824141
[patent_doc_number] => 05122985
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-16
[patent_title] => 'Circuit and method for erasing EEPROM memory arrays to prevent over-erased cells'
[patent_app_type] => 1
[patent_app_number] => 7/509432
[patent_app_country] => US
[patent_app_date] => 1990-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5025
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/122/05122985.pdf
[firstpage_image] =>[orig_patent_app_number] => 509432
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/509432 | Circuit and method for erasing EEPROM memory arrays to prevent over-erased cells | Apr 15, 1990 | Issued |