Search

Jae Kyun Woo

Examiner (ID: 2020, Phone: (571)272-0837 , Office: P/3779 )

Most Active Art Unit
3795
Art Unit(s)
3779, 3795
Total Applications
586
Issued Applications
326
Pending Applications
65
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11132329 [patent_doc_number] => 20160329305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'STACKED PACKAGE DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/015919 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2708 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015919 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015919
Stacked package device and method for fabricating the same Feb 3, 2016 Issued
Array ( [id] => 15286539 [patent_doc_number] => 10515939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method [patent_app_type] => utility [patent_app_number] => 15/015110 [patent_app_country] => US [patent_app_date] => 2016-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11257 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015110
Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method Feb 2, 2016 Issued
Array ( [id] => 11307580 [patent_doc_number] => 09514984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 15/011831 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 4160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011831
Semiconductor device and method for manufacturing same Jan 31, 2016 Issued
Array ( [id] => 11079337 [patent_doc_number] => 20160276301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'WIRING SUBSTRATE AND ELECTRONIC COMPONENT DEVICE' [patent_app_type] => utility [patent_app_number] => 15/012017 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5751 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012017
Wiring substrate and electronic component device Jan 31, 2016 Issued
Array ( [id] => 11071270 [patent_doc_number] => 20160268233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'SEMICONDUCTOR PACKAGE ASSEMBLY WITH PASSIVE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/012018 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5171 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012018
Semiconductor package assembly with passive device Jan 31, 2016 Issued
Array ( [id] => 11017904 [patent_doc_number] => 20160214857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'Semiconductor Device and Method of Forming MEMS Package' [patent_app_type] => utility [patent_app_number] => 15/008347 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20748 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008347
Semiconductor device and method of forming MEMS package Jan 26, 2016 Issued
Array ( [id] => 11028751 [patent_doc_number] => 20160225706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/008247 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 6280 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008247
PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Jan 26, 2016 Abandoned
Array ( [id] => 10795098 [patent_doc_number] => 20160141256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/003820 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7021 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003820 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/003820
Method for manufacturing a semiconductor device, and semiconductor device Jan 21, 2016 Issued
Array ( [id] => 10780073 [patent_doc_number] => 20160126229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'SEMICONDUCTOR CHIP AND A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) STRUCTURE INCLUDING THE SEMICONDUCTOR CHIP' [patent_app_type] => utility [patent_app_number] => 14/992174 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8709 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992174 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992174
Semiconductor chip and a semiconductor package having a package on package (POP) structure including the semiconductor chip Jan 10, 2016 Issued
Array ( [id] => 11681324 [patent_doc_number] => 09679859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Interconnect structure and method of forming same' [patent_app_type] => utility [patent_app_number] => 14/991560 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4682 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991560 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/991560
Interconnect structure and method of forming same Jan 7, 2016 Issued
Array ( [id] => 11787620 [patent_doc_number] => 09397082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Multiple die lead frame packaging' [patent_app_type] => utility [patent_app_number] => 14/990468 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990468
Multiple die lead frame packaging Jan 6, 2016 Issued
Array ( [id] => 13562321 [patent_doc_number] => 20180332708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => VERTICALLY EMBEDDED PASSIVE COMPONENTS [patent_app_type] => utility [patent_app_number] => 15/774263 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15774263 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/774263
VERTICALLY EMBEDDED PASSIVE COMPONENTS Dec 25, 2015 Abandoned
Array ( [id] => 12141293 [patent_doc_number] => 20180019376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'PROCESS FOR FABRICATING SEMICONDUCTOR NANOWIRES OR MICROWIRES HAVING INSULATED ROOTS' [patent_app_type] => utility [patent_app_number] => 15/538148 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4185 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15538148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/538148
Process for fabricating semiconductor nanowires or microwires having insulated roots Dec 23, 2015 Issued
Array ( [id] => 16553063 [patent_doc_number] => 10886228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Improving size and efficiency of dies [patent_app_type] => utility [patent_app_number] => 15/774091 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4394 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15774091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/774091
Improving size and efficiency of dies Dec 22, 2015 Issued
Array ( [id] => 12129486 [patent_doc_number] => 20180013072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'ORGANIC ELECTROLUMINESCENT ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/538781 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7529 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15538781 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/538781
Organic electroluminescent element Dec 20, 2015 Issued
Array ( [id] => 11286520 [patent_doc_number] => 09502380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Three dimensional integrated circuits stacking approach' [patent_app_type] => utility [patent_app_number] => 14/959094 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959094 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/959094
Three dimensional integrated circuits stacking approach Dec 3, 2015 Issued
Array ( [id] => 13419949 [patent_doc_number] => 20180261517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/758349 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15758349 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/758349
Power semiconductor device Dec 3, 2015 Issued
Array ( [id] => 11180915 [patent_doc_number] => 09412915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Lighting apparatus' [patent_app_type] => utility [patent_app_number] => 14/942735 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4775 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942735 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942735
Lighting apparatus Nov 15, 2015 Issued
Array ( [id] => 11253007 [patent_doc_number] => 09478519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Package including a semiconductor die and a capacitive component' [patent_app_type] => utility [patent_app_number] => 14/927871 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 25710 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927871 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/927871
Package including a semiconductor die and a capacitive component Oct 29, 2015 Issued
Array ( [id] => 10747684 [patent_doc_number] => 20160093835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Semiconductor Device and Method of Manufacturing Same' [patent_app_type] => utility [patent_app_number] => 14/883939 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13373 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/883939
Semiconductor device and method of manufacturing same Oct 14, 2015 Issued
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