
Jae Lee
Examiner (ID: 1955, Phone: (571)270-1224 , Office: P/2899 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2895, 2823, 2899 |
| Total Applications | 951 |
| Issued Applications | 742 |
| Pending Applications | 2 |
| Abandoned Applications | 207 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5465162
[patent_doc_number] => 20090325362
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'METHOD OF RECYCLING AN EPITAXIED DONOR WAFER'
[patent_app_type] => utility
[patent_app_number] => 12/503537
[patent_app_country] => US
[patent_app_date] => 2009-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6299
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0325/20090325362.pdf
[firstpage_image] =>[orig_patent_app_number] => 12503537
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/503537 | METHOD OF RECYCLING AN EPITAXIED DONOR WAFER | Jul 14, 2009 | Abandoned |
Array
(
[id] => 8690511
[patent_doc_number] => 08390040
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-05
[patent_title] => 'Localized spacer for a multi-gate transistor'
[patent_app_type] => utility
[patent_app_number] => 12/500655
[patent_app_country] => US
[patent_app_date] => 2009-07-10
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12500655
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/500655 | Localized spacer for a multi-gate transistor | Jul 9, 2009 | Issued |
Array
(
[id] => 6372536
[patent_doc_number] => 20100300743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-02
[patent_title] => 'Modified Pillar Design for Improved Flip Chip Packaging'
[patent_app_type] => utility
[patent_app_number] => 12/476928
[patent_app_country] => US
[patent_app_date] => 2009-06-02
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0300/20100300743.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/476928 | Modified Pillar Design for Improved Flip Chip Packaging | Jun 1, 2009 | Abandoned |
Array
(
[id] => 5488289
[patent_doc_number] => 20090289360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'WORKPIECE CONTACT PADS WITH ELEVATED RING FOR RESTRICTING HORIZONTAL MOVEMENT OF TERMINALS OF IC DURING PRESSING'
[patent_app_type] => utility
[patent_app_number] => 12/470004
[patent_app_country] => US
[patent_app_date] => 2009-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0289/20090289360.pdf
[firstpage_image] =>[orig_patent_app_number] => 12470004
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/470004 | WORKPIECE CONTACT PADS WITH ELEVATED RING FOR RESTRICTING HORIZONTAL MOVEMENT OF TERMINALS OF IC DURING PRESSING | May 20, 2009 | Abandoned |
Array
(
[id] => 6336917
[patent_doc_number] => 20100019386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/469883
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[patent_app_date] => 2009-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0019/20100019386.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/469883 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | May 20, 2009 | Abandoned |
Array
(
[id] => 8549138
[patent_doc_number] => 08324019
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-04
[patent_title] => 'Solution for package crosstalk minimization'
[patent_app_type] => utility
[patent_app_number] => 12/469985
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/469985 | Solution for package crosstalk minimization | May 20, 2009 | Issued |
Array
(
[id] => 5488280
[patent_doc_number] => 20090289351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'Semiconductor apparatus having both-side heat radiation structure and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/453784
[patent_app_country] => US
[patent_app_date] => 2009-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => publications/A1/0289/20090289351.pdf
[firstpage_image] =>[orig_patent_app_number] => 12453784
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/453784 | Semiconductor apparatus having a two-side heat radiation structure | May 20, 2009 | Issued |
Array
(
[id] => 5490453
[patent_doc_number] => 20090291524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'COMBINED METALLIC BONDING AND MOLDING FOR ELECTRONIC ASSEMBLIES INCLUDING VOID-REDUCED UNDERFILL'
[patent_app_type] => utility
[patent_app_number] => 12/469935
[patent_app_country] => US
[patent_app_date] => 2009-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0291/20090291524.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/469935 | Combined metallic bonding and molding for electronic assemblies including void-reduced underfill | May 20, 2009 | Issued |
Array
(
[id] => 8422193
[patent_doc_number] => 08278681
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[patent_kind] => B2
[patent_issue_date] => 2012-10-02
[patent_title] => 'Light-emitting diode package and wafer-level packaging process of light-emitting diode'
[patent_app_type] => utility
[patent_app_number] => 12/469669
[patent_app_country] => US
[patent_app_date] => 2009-05-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/469669 | Light-emitting diode package and wafer-level packaging process of light-emitting diode | May 19, 2009 | Issued |
Array
(
[id] => 5549325
[patent_doc_number] => 20090283311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-19
[patent_title] => 'Electronic element wafer module and method for manufacturing electronic element wafer module, electronic element module, and electronic information device'
[patent_app_type] => utility
[patent_app_number] => 12/387433
[patent_app_country] => US
[patent_app_date] => 2009-05-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/387433 | Electronic element wafer module and method for manufacturing electronic element wafer module, electronic element module, and electronic information device | Apr 30, 2009 | Abandoned |
Array
(
[id] => 8543234
[patent_doc_number] => 08318523
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[patent_issue_date] => 2012-11-27
[patent_title] => 'Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same'
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Array
(
[id] => 5483611
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[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'AC/DC CONVERTERS AND METHODS OF MANUFACTURING SAME'
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Array
(
[id] => 6462894
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/314507 | Thin film transistor and method of fabricating the same | Dec 10, 2008 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/323978 | Methods of forming diodes | Nov 25, 2008 | Issued |
Array
(
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[patent_title] => 'Backside nitride removal to reduce streak defects'
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Array
(
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Array
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Array
(
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