Search

Jae Lee

Examiner (ID: 1955, Phone: (571)270-1224 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2895, 2823, 2899
Total Applications
951
Issued Applications
742
Pending Applications
2
Abandoned Applications
207

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5552345 [patent_doc_number] => 20090286331 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2009-11-19 [patent_title] => 'METHOD FOR SIMULATENOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY' [patent_app_type] => utility [patent_app_number] => 12/267711 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15180 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A2/0286/20090286331.pdf [firstpage_image] =>[orig_patent_app_number] => 12267711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267711
METHOD FOR SIMULTANEOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY Nov 9, 2008 Abandoned
Array ( [id] => 5552345 [patent_doc_number] => 20090286331 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2009-11-19 [patent_title] => 'METHOD FOR SIMULATENOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY' [patent_app_type] => utility [patent_app_number] => 12/267711 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15180 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A2/0286/20090286331.pdf [firstpage_image] =>[orig_patent_app_number] => 12267711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267711
METHOD FOR SIMULATENOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY Nov 9, 2008 Abandoned
Array ( [id] => 7685899 [patent_doc_number] => 20100120242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD TO PREVENT LOCALIZED ELECTRICAL OPEN CU LEADS IN VLSI CU INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 12/266596 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20100120242.pdf [firstpage_image] =>[orig_patent_app_number] => 12266596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/266596
METHOD TO PREVENT LOCALIZED ELECTRICAL OPEN CU LEADS IN VLSI CU INTERCONNECTS Nov 6, 2008 Abandoned
Array ( [id] => 5265025 [patent_doc_number] => 20090117710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD OF CUTTING SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP APPARATUS, AND CHAMBER TO CUT WAFER' [patent_app_type] => utility [patent_app_number] => 12/265165 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4891 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20090117710.pdf [firstpage_image] =>[orig_patent_app_number] => 12265165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265165
Method of cutting semiconductor wafer, semiconductor chip apparatus, and chamber to cut wafer Nov 4, 2008 Issued
Array ( [id] => 6586414 [patent_doc_number] => 20100308476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/734695 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4524 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20100308476.pdf [firstpage_image] =>[orig_patent_app_number] => 12734695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/734695
Method for manufacturing semiconductor device Oct 29, 2008 Issued
Array ( [id] => 8871124 [patent_doc_number] => 08466503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Semiconductor transistors with expanded top portions of gates' [patent_app_type] => utility [patent_app_number] => 12/189298 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 4217 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12189298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/189298
Semiconductor transistors with expanded top portions of gates Aug 10, 2008 Issued
Array ( [id] => 4960146 [patent_doc_number] => 20080274571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Semiconductor device, LED print head and image-forming apparatus using same, and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/165699 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 13711 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20080274571.pdf [firstpage_image] =>[orig_patent_app_number] => 12165699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165699
Semiconductor device, LED print head and image-forming apparatus using same, and method of manufacturing semiconductor device Jun 30, 2008 Issued
Array ( [id] => 5465191 [patent_doc_number] => 20090325391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'OZONE AND TEOS PROCESS FOR SILICON OXIDE DEPOSITION' [patent_app_type] => utility [patent_app_number] => 12/165497 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5674 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20090325391.pdf [firstpage_image] =>[orig_patent_app_number] => 12165497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165497
OZONE AND TEOS PROCESS FOR SILICON OXIDE DEPOSITION Jun 29, 2008 Abandoned
Array ( [id] => 7503282 [patent_doc_number] => 08034674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Semiconductor device, method for manufacturing semiconductor device, and electronic appliance' [patent_app_type] => utility [patent_app_number] => 12/163227 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 40 [patent_no_of_words] => 11622 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/034/08034674.pdf [firstpage_image] =>[orig_patent_app_number] => 12163227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163227
Semiconductor device, method for manufacturing semiconductor device, and electronic appliance Jun 26, 2008 Issued
Array ( [id] => 7712065 [patent_doc_number] => 08093122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Method for fabricating vertical channel transistor' [patent_app_type] => utility [patent_app_number] => 12/163257 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2032 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093122.pdf [firstpage_image] =>[orig_patent_app_number] => 12163257 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163257
Method for fabricating vertical channel transistor Jun 26, 2008 Issued
Array ( [id] => 7801542 [patent_doc_number] => 08129816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/142326 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6819 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129816.pdf [firstpage_image] =>[orig_patent_app_number] => 12142326 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142326
Semiconductor device and method of manufacturing the same Jun 18, 2008 Issued
Array ( [id] => 5262214 [patent_doc_number] => 20090114899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'RESISTANCE MEMORY AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/141966 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20090114899.pdf [firstpage_image] =>[orig_patent_app_number] => 12141966 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141966
RESISTANCE MEMORY AND METHOD FOR MANUFACTURING THE SAME Jun 18, 2008 Abandoned
Array ( [id] => 5319919 [patent_doc_number] => 20090057909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION' [patent_app_type] => utility [patent_app_number] => 12/142415 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3239 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057909.pdf [firstpage_image] =>[orig_patent_app_number] => 12142415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142415
UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION Jun 18, 2008 Abandoned
Array ( [id] => 4849596 [patent_doc_number] => 20080315338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/141140 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2312 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315338.pdf [firstpage_image] =>[orig_patent_app_number] => 12141140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141140
IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME Jun 17, 2008 Abandoned
Array ( [id] => 4849563 [patent_doc_number] => 20080315305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/141386 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4509 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315305.pdf [firstpage_image] =>[orig_patent_app_number] => 12141386 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141386
Semiconductor device and method of manufacturing the same Jun 17, 2008 Issued
Array ( [id] => 4719545 [patent_doc_number] => 20080242068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/137807 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6320 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242068.pdf [firstpage_image] =>[orig_patent_app_number] => 12137807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137807
Method for manufacturing a semiconductor device Jun 11, 2008 Issued
Array ( [id] => 8421653 [patent_doc_number] => 08278141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Integrated circuit package system with internal stacking module' [patent_app_type] => utility [patent_app_number] => 12/137529 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6268 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12137529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137529
Integrated circuit package system with internal stacking module Jun 10, 2008 Issued
Array ( [id] => 5367904 [patent_doc_number] => 20090305463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'System and Method for Thermal Optimized Chip Stacking' [patent_app_type] => utility [patent_app_number] => 12/134728 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1877 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20090305463.pdf [firstpage_image] =>[orig_patent_app_number] => 12134728 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134728
System and Method for Thermal Optimized Chip Stacking Jun 5, 2008 Abandoned
Array ( [id] => 8410242 [patent_doc_number] => 08273639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Atomic layer deposition method and semiconductor device formed by the same' [patent_app_type] => utility [patent_app_number] => 12/132459 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6457 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12132459 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132459
Atomic layer deposition method and semiconductor device formed by the same Jun 2, 2008 Issued
Array ( [id] => 5342866 [patent_doc_number] => 20090181516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'Method of Forming Isolation Layer of Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/131239 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2342 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20090181516.pdf [firstpage_image] =>[orig_patent_app_number] => 12131239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131239
Method of Forming Isolation Layer of Semiconductor Device Jun 1, 2008 Abandoned
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