Search

Jae Lee

Examiner (ID: 1955, Phone: (571)270-1224 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2895, 2823, 2899
Total Applications
951
Issued Applications
742
Pending Applications
2
Abandoned Applications
207

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8577636 [patent_doc_number] => 08343846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Method of forming isolation layer in semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/131229 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6206 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12131229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131229
Method of forming isolation layer in semiconductor device Jun 1, 2008 Issued
Array ( [id] => 5567336 [patent_doc_number] => 20090250714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'White light emitting diode and lighting apparatus using the same' [patent_app_type] => utility [patent_app_number] => 12/155276 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3029 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20090250714.pdf [firstpage_image] =>[orig_patent_app_number] => 12155276 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155276
White light emitting diode and lighting apparatus using the same Jun 1, 2008 Abandoned
Array ( [id] => 8410749 [patent_doc_number] => 08274146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'High frequency interconnect pad structure' [patent_app_type] => utility [patent_app_number] => 12/130579 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4776 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12130579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130579
High frequency interconnect pad structure May 29, 2008 Issued
Array ( [id] => 4708039 [patent_doc_number] => 20080296565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'METHOD OF FABRICATING POLYCRYSTALLINE SILICON LAYER, TFT FABRICATED USING THE SAME, METHOD OF FABRICATING TFT, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/130340 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8542 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296565.pdf [firstpage_image] =>[orig_patent_app_number] => 12130340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130340
METHOD OF FABRICATING POLYCRYSTALLINE SILICON LAYER, TFT FABRICATED USING THE SAME, METHOD OF FABRICATING TFT, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME May 29, 2008 Abandoned
Array ( [id] => 5361091 [patent_doc_number] => 20090035885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'METHODS OF FORMING LIGHT-EMITTING STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/130899 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5927 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035885.pdf [firstpage_image] =>[orig_patent_app_number] => 12130899 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130899
Methods of forming light-emitting structures May 29, 2008 Issued
Array ( [id] => 5300198 [patent_doc_number] => 20090294850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/130460 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6864 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294850.pdf [firstpage_image] =>[orig_patent_app_number] => 12130460 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130460
Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device May 29, 2008 Issued
Array ( [id] => 10172066 [patent_doc_number] => 09202777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Semiconductor package system with cut multiple lead pads' [patent_app_type] => utility [patent_app_number] => 12/131037 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 8189 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12131037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131037
Semiconductor package system with cut multiple lead pads May 29, 2008 Issued
Array ( [id] => 5330781 [patent_doc_number] => 20090111258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Method for Manufacturing a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/129769 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2914 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20090111258.pdf [firstpage_image] =>[orig_patent_app_number] => 12129769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129769
Method for manufacturing a semiconductor device May 29, 2008 Issued
Array ( [id] => 5300334 [patent_doc_number] => 20090294986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Methods of Forming Conductive Features and Structures Thereof' [patent_app_type] => utility [patent_app_number] => 12/129479 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8676 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294986.pdf [firstpage_image] =>[orig_patent_app_number] => 12129479 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129479
Methods of forming conductive features and structures thereof May 28, 2008 Issued
Array ( [id] => 4485620 [patent_doc_number] => 07883941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Methods for fabricating memory cells and memory devices incorporating the same' [patent_app_type] => utility [patent_app_number] => 12/128908 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 11245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883941.pdf [firstpage_image] =>[orig_patent_app_number] => 12128908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128908
Methods for fabricating memory cells and memory devices incorporating the same May 28, 2008 Issued
Array ( [id] => 4756686 [patent_doc_number] => 20080308911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/125967 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17245 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20080308911.pdf [firstpage_image] =>[orig_patent_app_number] => 12125967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125967
Method of manufacturing for thin film transistor May 22, 2008 Issued
Array ( [id] => 5488308 [patent_doc_number] => 20090289379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Methods of Manufacturing Semiconductor Devices and Structures Thereof' [patent_app_type] => utility [patent_app_number] => 12/125238 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8944 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20090289379.pdf [firstpage_image] =>[orig_patent_app_number] => 12125238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125238
Methods of manufacturing semiconductor devices and structures thereof May 21, 2008 Issued
Array ( [id] => 4792254 [patent_doc_number] => 20080293228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'CMOS Compatible Method of Forming Source/Drain Contacts for Self-Aligned Nanotube Devices' [patent_app_type] => utility [patent_app_number] => 12/124827 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2492 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20080293228.pdf [firstpage_image] =>[orig_patent_app_number] => 12124827 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124827
CMOS Compatible Method of Forming Source/Drain Contacts for Self-Aligned Nanotube Devices May 20, 2008 Abandoned
Array ( [id] => 5488127 [patent_doc_number] => 20090289198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'SYSTEMS AND METHODS FOR ACOUSTIC SENSING' [patent_app_type] => utility [patent_app_number] => 12/123628 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4945 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20090289198.pdf [firstpage_image] =>[orig_patent_app_number] => 12123628 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123628
Systems and methods for acoustic sensing May 19, 2008 Issued
Array ( [id] => 4698434 [patent_doc_number] => 20080220618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'ZIRCONIUM SILICON OXIDE FILMS' [patent_app_type] => utility [patent_app_number] => 12/124047 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10661 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20080220618.pdf [firstpage_image] =>[orig_patent_app_number] => 12124047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124047
ZIRCONIUM SILICON OXIDE FILMS May 19, 2008 Abandoned
Array ( [id] => 5549931 [patent_doc_number] => 20090283917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'SYSTEMS AND METHODS FOR VERTICAL STACKED SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/123127 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3732 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283917.pdf [firstpage_image] =>[orig_patent_app_number] => 12123127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123127
SYSTEMS AND METHODS FOR VERTICAL STACKED SEMICONDUCTOR DEVICES May 18, 2008 Abandoned
Array ( [id] => 5452740 [patent_doc_number] => 20090068777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'METHOD FOR MANUFACTURING PIXEL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/121777 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4126 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068777.pdf [firstpage_image] =>[orig_patent_app_number] => 12121777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121777
METHOD FOR MANUFACTURING PIXEL STRUCTURE May 14, 2008 Abandoned
Array ( [id] => 8802296 [patent_doc_number] => 08440570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/116367 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2067 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12116367 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/116367
Method for manufacturing semiconductor device May 6, 2008 Issued
Array ( [id] => 5327859 [patent_doc_number] => 20090108336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/115627 [patent_app_country] => US [patent_app_date] => 2008-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108336.pdf [firstpage_image] =>[orig_patent_app_number] => 12115627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/115627
METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE May 5, 2008 Abandoned
Array ( [id] => 4570881 [patent_doc_number] => 07847400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Semiconductor package substrate structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/114517 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 3548 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847400.pdf [firstpage_image] =>[orig_patent_app_number] => 12114517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114517
Semiconductor package substrate structure and manufacturing method thereof May 1, 2008 Issued
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