
Jae Lee
Examiner (ID: 1955, Phone: (571)270-1224 , Office: P/2899 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2895, 2823, 2899 |
| Total Applications | 951 |
| Issued Applications | 742 |
| Pending Applications | 2 |
| Abandoned Applications | 207 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5730234
[patent_doc_number] => 20060255348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/164133
[patent_app_country] => US
[patent_app_date] => 2005-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3783
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0255/20060255348.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164133
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164133 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF | Nov 10, 2005 | Abandoned |
Array
(
[id] => 5670266
[patent_doc_number] => 20060175620
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-10
[patent_title] => 'Epitaxial wafer for light emitting diode'
[patent_app_type] => utility
[patent_app_number] => 11/269563
[patent_app_country] => US
[patent_app_date] => 2005-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3945
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20060175620.pdf
[firstpage_image] =>[orig_patent_app_number] => 11269563
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/269563 | Epitaxial wafer for light emitting diode | Nov 8, 2005 | Abandoned |
Array
(
[id] => 5921913
[patent_doc_number] => 20060240285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-26
[patent_title] => 'Organic electroluminescent device'
[patent_app_type] => utility
[patent_app_number] => 11/266303
[patent_app_country] => US
[patent_app_date] => 2005-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8891
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0240/20060240285.pdf
[firstpage_image] =>[orig_patent_app_number] => 11266303
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/266303 | Organic electroluminescent device | Nov 3, 2005 | Issued |
Array
(
[id] => 177814
[patent_doc_number] => 07655522
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Metal oxide semiconductor (MOS) transistor having a recessed gate electrode and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/263434
[patent_app_country] => US
[patent_app_date] => 2005-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 5992
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/655/07655522.pdf
[firstpage_image] =>[orig_patent_app_number] => 11263434
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/263434 | Metal oxide semiconductor (MOS) transistor having a recessed gate electrode and methods of fabricating the same | Oct 30, 2005 | Issued |
Array
(
[id] => 5838135
[patent_doc_number] => 20060118793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Thin film transistor array panel and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/262163
[patent_app_country] => US
[patent_app_date] => 2005-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 8626
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0118/20060118793.pdf
[firstpage_image] =>[orig_patent_app_number] => 11262163
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/262163 | Thin film transistor array panel and method for manufacturing the same | Oct 26, 2005 | Abandoned |
Array
(
[id] => 5810466
[patent_doc_number] => 20060081574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-20
[patent_title] => 'Wafer dividing apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/249494
[patent_app_country] => US
[patent_app_date] => 2005-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7072
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20060081574.pdf
[firstpage_image] =>[orig_patent_app_number] => 11249494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/249494 | Wafer dividing apparatus | Oct 13, 2005 | Issued |
Array
(
[id] => 5038102
[patent_doc_number] => 20070090384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'Nitride based semiconductor device having multiple layer buffer structure and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/244737
[patent_app_country] => US
[patent_app_date] => 2005-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2351
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20070090384.pdf
[firstpage_image] =>[orig_patent_app_number] => 11244737
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/244737 | Nitride based semiconductor device having multiple layer buffer structure and fabrication method thereof | Oct 5, 2005 | Abandoned |
Array
(
[id] => 5247420
[patent_doc_number] => 20070243654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'Microelectromechanical device with integrated conductive shield'
[patent_app_type] => utility
[patent_app_number] => 11/237104
[patent_app_country] => US
[patent_app_date] => 2005-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7763
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0243/20070243654.pdf
[firstpage_image] =>[orig_patent_app_number] => 11237104
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/237104 | Microelectromechanical device with integrated conductive shield | Sep 27, 2005 | Issued |
Array
(
[id] => 5912505
[patent_doc_number] => 20060127567
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/235634
[patent_app_country] => US
[patent_app_date] => 2005-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10260
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20060127567.pdf
[firstpage_image] =>[orig_patent_app_number] => 11235634
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/235634 | Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device | Sep 25, 2005 | Issued |
Array
(
[id] => 5104401
[patent_doc_number] => 20070063276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/162663
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 8680
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20070063276.pdf
[firstpage_image] =>[orig_patent_app_number] => 11162663
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162663 | Dense chevron finFET and method of manufacturing same | Sep 18, 2005 | Issued |
Array
(
[id] => 856695
[patent_doc_number] => 07374954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-20
[patent_title] => 'Ferroelectric register, and method for manufacturing capacitor of the same'
[patent_app_type] => utility
[patent_app_number] => 11/227084
[patent_app_country] => US
[patent_app_date] => 2005-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 4784
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/374/07374954.pdf
[firstpage_image] =>[orig_patent_app_number] => 11227084
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/227084 | Ferroelectric register, and method for manufacturing capacitor of the same | Sep 15, 2005 | Issued |
Array
(
[id] => 4947043
[patent_doc_number] => 20080303169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'Integrated Circuit Arrangment Including Vias Having Two Sections, and Method For Producing the Same'
[patent_app_type] => utility
[patent_app_number] => 11/575385
[patent_app_country] => US
[patent_app_date] => 2005-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4621
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0303/20080303169.pdf
[firstpage_image] =>[orig_patent_app_number] => 11575385
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/575385 | Integrated circuit arrangement including vias having two sections, and method for producing the same | Aug 24, 2005 | Issued |
Array
(
[id] => 5599602
[patent_doc_number] => 20060289947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-28
[patent_title] => 'Semiconductor device and its manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 10/577457
[patent_app_country] => US
[patent_app_date] => 2005-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12522
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20060289947.pdf
[firstpage_image] =>[orig_patent_app_number] => 10577457
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/577457 | Semiconductor device | Aug 2, 2005 | Issued |
Array
(
[id] => 10507538
[patent_doc_number] => 09235413
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-01-12
[patent_title] => 'Automated control of semiconductor wafer manufacturing based on electrical test results'
[patent_app_type] => utility
[patent_app_number] => 11/196364
[patent_app_country] => US
[patent_app_date] => 2005-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4612
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11196364
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/196364 | Automated control of semiconductor wafer manufacturing based on electrical test results | Aug 2, 2005 | Issued |
Array
(
[id] => 5154194
[patent_doc_number] => 20070037077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Substrate holder and device manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/195864
[patent_app_country] => US
[patent_app_date] => 2005-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5316
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20070037077.pdf
[firstpage_image] =>[orig_patent_app_number] => 11195864
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/195864 | Substrate holder and device manufacturing method | Aug 2, 2005 | Issued |
Array
(
[id] => 359663
[patent_doc_number] => 07485542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Method for producing bit lines for UCP flash memories'
[patent_app_type] => utility
[patent_app_number] => 11/194059
[patent_app_country] => US
[patent_app_date] => 2005-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 17
[patent_no_of_words] => 1656
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/485/07485542.pdf
[firstpage_image] =>[orig_patent_app_number] => 11194059
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/194059 | Method for producing bit lines for UCP flash memories | Jul 28, 2005 | Issued |
Array
(
[id] => 5205091
[patent_doc_number] => 20070026573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Method of making a stacked die package'
[patent_app_type] => utility
[patent_app_number] => 11/193144
[patent_app_country] => US
[patent_app_date] => 2005-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4859
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20070026573.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193144
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193144 | Method of making a stacked die package | Jul 27, 2005 | Abandoned |
Array
(
[id] => 5820619
[patent_doc_number] => 20060024932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'Methods of forming semiconductor devices including removing a thickness of a polysilicon gate layer'
[patent_app_type] => utility
[patent_app_number] => 11/191488
[patent_app_country] => US
[patent_app_date] => 2005-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4903
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20060024932.pdf
[firstpage_image] =>[orig_patent_app_number] => 11191488
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/191488 | Methods of forming semiconductor devices including removing a thickness of a polysilicon gate layer | Jul 27, 2005 | Abandoned |
Array
(
[id] => 5202317
[patent_doc_number] => 20070023796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'PINNING LAYER FOR PIXEL SENSOR CELL AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/161224
[patent_app_country] => US
[patent_app_date] => 2005-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3965
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20070023796.pdf
[firstpage_image] =>[orig_patent_app_number] => 11161224
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161224 | PINNING LAYER FOR PIXEL SENSOR CELL AND METHOD THEREOF | Jul 26, 2005 | Abandoned |
Array
(
[id] => 5205154
[patent_doc_number] => 20070026636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Wide and narrow trench formation in high aspect ratio MEMS'
[patent_app_type] => utility
[patent_app_number] => 11/192198
[patent_app_country] => US
[patent_app_date] => 2005-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5573
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20070026636.pdf
[firstpage_image] =>[orig_patent_app_number] => 11192198
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/192198 | Wide and narrow trench formation in high aspect ratio MEMS | Jul 26, 2005 | Issued |