Jae Un Yu

Array ( [id] => 20580225 [patent_doc_number] => 12572476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => GPU chiplets using high bandwidth crosslinks [patent_app_type] => utility [patent_app_number] => 19/337250 [patent_app_country] => US [patent_app_date] => 2025-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19337250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20680225 [patent_doc_number] => 20260119042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => DEVICE AND METHOD WITH HOTNESS TRACKING [patent_app_type] => utility [patent_app_number] => 19/266807 [patent_app_country] => US [patent_app_date] => 2025-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19266807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20487301 [patent_doc_number] => 20260023500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => DELAYED EXECUTION OF A MULTIPLE-READ OPERATION [patent_app_type] => utility [patent_app_number] => 19/261048 [patent_app_country] => US [patent_app_date] => 2025-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19261048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20296647 [patent_doc_number] => 20250321890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => EFFICIENT KEY-VALUE CACHE MANAGEMENT FOR LARGE LANGUAGE MODELS [patent_app_type] => utility [patent_app_number] => 19/248613 [patent_app_country] => US [patent_app_date] => 2025-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19248613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20474734 [patent_doc_number] => 20260016955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => MEMORY SUB-SYSTEM FOR PERFORMING BLOCK STRIPE MANAGEMENT USING RATE CONTROL [patent_app_type] => utility [patent_app_number] => 19/241227 [patent_app_country] => US [patent_app_date] => 2025-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19241227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20421910 [patent_doc_number] => 20250383995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => LOGICAL TO PHYSICAL (L2P) MANAGEMENT FOR FOLDING OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 19/236515 [patent_app_country] => US [patent_app_date] => 2025-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19236515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20395156 [patent_doc_number] => 20250370631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY SUB-SYSTEM FOR ALLOCATING BLOCK STRIPES BASED ON PROGRAM ERASE CYCLES [patent_app_type] => utility [patent_app_number] => 19/219941 [patent_app_country] => US [patent_app_date] => 2025-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19219941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181242 [patent_doc_number] => 20250265200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => VICTIM CACHE WITH WRITE MISS MERGING [patent_app_type] => utility [patent_app_number] => 19/199722 [patent_app_country] => US [patent_app_date] => 2025-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19199722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20513031 [patent_doc_number] => 20260037132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => SYSTEMS AND METHODS FOR MULTI-PRECISION MEMORY RETRIEVAL [patent_app_type] => utility [patent_app_number] => 19/200446 [patent_app_country] => US [patent_app_date] => 2025-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19200446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181235 [patent_doc_number] => 20250265193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => HARDWARE COHERENCE FOR MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 19/199662 [patent_app_country] => US [patent_app_date] => 2025-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19199662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20095134 [patent_doc_number] => 20250225070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => NEURAL PROCESSING DEVICE AND METHOD FOR TRANSMITTING DATA THEREOF [patent_app_type] => utility [patent_app_number] => 19/093091 [patent_app_country] => US [patent_app_date] => 2025-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19093091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20513077 [patent_doc_number] => 20260037178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => DATA STORAGE METHOD AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 19/082135 [patent_app_country] => US [patent_app_date] => 2025-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19082135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20570392 [patent_doc_number] => 20260064316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 19/078391 [patent_app_country] => US [patent_app_date] => 2025-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19078391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20543506 [patent_doc_number] => 20260050397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => SOLID-STATE DRIVE WITH HIGH-SPEED DATA BUFFERING [patent_app_type] => utility [patent_app_number] => 19/075388 [patent_app_country] => US [patent_app_date] => 2025-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19075388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20601630 [patent_doc_number] => 20260079639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 19/070637 [patent_app_country] => US [patent_app_date] => 2025-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19070637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20601636 [patent_doc_number] => 20260079645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 19/060872 [patent_app_country] => US [patent_app_date] => 2025-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20208479 [patent_doc_number] => 20250278199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => VARIABLE-LENGTH CONSTRAINT ENCODING TO IMPROVE ENDURANCE [patent_app_type] => utility [patent_app_number] => 19/060221 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20195536 [patent_doc_number] => 20250272246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => PROCESSING CACHE EVICTIONS IN A DIRECTORY SNOOP FILTER WITH ECAM [patent_app_type] => utility [patent_app_number] => 19/059355 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19059355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20249866 [patent_doc_number] => 20250298735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INTERLEAVED MEMORY TRANSACTION TRACKING FOR TRANSACTIONS WITH UNRELATED LENGTHS [patent_app_type] => utility [patent_app_number] => 19/059031 [patent_app_country] => US [patent_app_date] => 2025-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19059031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20914056 [patent_doc_number] => 12710901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Implementing coherency and page cache support in a distributed way for files [patent_app_type] => utility [patent_app_number] => 19/045014 [patent_app_country] => US [patent_app_date] => 2025-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19045014 [rel_patent_id] =>[rel_patent_doc_number] =>)