Search

Jafar F. Parsa

Examiner (ID: 11740, Phone: (571)272-0643 , Office: P/1671 )

Most Active Art Unit
1621
Art Unit(s)
1671, 1621, 1622, 1692
Total Applications
2798
Issued Applications
2233
Pending Applications
309
Abandoned Applications
289

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4443348 [patent_doc_number] => 07900037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-01 [patent_title] => 'Disk drive maintaining multiple logs to expedite boot operation for a host computer' [patent_app_type] => utility [patent_app_number] => 12/030074 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2669 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900037.pdf [firstpage_image] =>[orig_patent_app_number] => 12030074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030074
Disk drive maintaining multiple logs to expedite boot operation for a host computer Feb 11, 2008 Issued
Array ( [id] => 11179398 [patent_doc_number] => 09411390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Integrated circuit device having power domains and partitions based on use case power optimization' [patent_app_type] => utility [patent_app_number] => 12/029404 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6873 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12029404 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/029404
Integrated circuit device having power domains and partitions based on use case power optimization Feb 10, 2008 Issued
Array ( [id] => 5481873 [patent_doc_number] => 20090204830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'POWER MANAGEMENT WITH DYNAMIC FREQUENCY DAJUSTMENTS' [patent_app_type] => utility [patent_app_number] => 12/029375 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20090204830.pdf [firstpage_image] =>[orig_patent_app_number] => 12029375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/029375
Power management with dynamic frequency adjustments Feb 10, 2008 Issued
Array ( [id] => 5481878 [patent_doc_number] => 20090204835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS' [patent_app_type] => utility [patent_app_number] => 12/029442 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6858 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20090204835.pdf [firstpage_image] =>[orig_patent_app_number] => 12029442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/029442
USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS Feb 10, 2008 Abandoned
Array ( [id] => 4821479 [patent_doc_number] => 20080122495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Automatic Calibration of a Reference Voltage' [patent_app_type] => utility [patent_app_number] => 12/028249 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122495.pdf [firstpage_image] =>[orig_patent_app_number] => 12028249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/028249
Automatic Calibration of a Reference Voltage Feb 7, 2008 Abandoned
Array ( [id] => 4592047 [patent_doc_number] => 07836317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Methods and apparatus for power control in a scalable array of processor elements' [patent_app_type] => utility [patent_app_number] => 12/021538 [patent_app_country] => US [patent_app_date] => 2008-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8689 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836317.pdf [firstpage_image] =>[orig_patent_app_number] => 12021538 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/021538
Methods and apparatus for power control in a scalable array of processor elements Jan 28, 2008 Issued
Array ( [id] => 4869018 [patent_doc_number] => 20080148077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'MEMORY CARD CONTROL APPARATUS AND PROTECTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/956324 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148077.pdf [firstpage_image] =>[orig_patent_app_number] => 11956324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956324
Memory card control apparatus and protection method thereof Dec 12, 2007 Issued
Array ( [id] => 7972217 [patent_doc_number] => 07941687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Method and apparatus for digital I/O expander chip with multi-function timer cells' [patent_app_type] => utility [patent_app_number] => 11/956121 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 50 [patent_no_of_words] => 6777 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941687.pdf [firstpage_image] =>[orig_patent_app_number] => 11956121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956121
Method and apparatus for digital I/O expander chip with multi-function timer cells Dec 12, 2007 Issued
Array ( [id] => 4559325 [patent_doc_number] => 07877622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Selecting between high availability redundant power supply modes for powering a computer system' [patent_app_type] => utility [patent_app_number] => 11/956247 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877622.pdf [firstpage_image] =>[orig_patent_app_number] => 11956247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956247
Selecting between high availability redundant power supply modes for powering a computer system Dec 12, 2007 Issued
Array ( [id] => 7686382 [patent_doc_number] => 20090177909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'MEMORY BUS SHARED SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/955664 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9654 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177909.pdf [firstpage_image] =>[orig_patent_app_number] => 11955664 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955664
Memory bus shared system Dec 12, 2007 Issued
Array ( [id] => 4573095 [patent_doc_number] => 07962775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Methods and apparatus for power mode control for PDA with separate communications and applications processors' [patent_app_type] => utility [patent_app_number] => 11/956088 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3089 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962775.pdf [firstpage_image] =>[orig_patent_app_number] => 11956088 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956088
Methods and apparatus for power mode control for PDA with separate communications and applications processors Dec 12, 2007 Issued
Array ( [id] => 5548144 [patent_doc_number] => 20090158021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHODS OF USING BIOS INFORMATION WHEN BOOTING INFORMATION HANDLING SYSTEMS AND MACHINE-EXECUTABLE CODE FOR CARRYING OUT THE METHODS' [patent_app_type] => utility [patent_app_number] => 11/955462 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158021.pdf [firstpage_image] =>[orig_patent_app_number] => 11955462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955462
Methods of using bios information when booting information handling systems and machine-executable code for carrying out the methods Dec 12, 2007 Issued
Array ( [id] => 4486797 [patent_doc_number] => 07870408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Universal serial bus wakeup circuit' [patent_app_type] => utility [patent_app_number] => 11/955153 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870408.pdf [firstpage_image] =>[orig_patent_app_number] => 11955153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955153
Universal serial bus wakeup circuit Dec 11, 2007 Issued
Array ( [id] => 116621 [patent_doc_number] => 07721135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Method of timing calibration using slower data rate pattern' [patent_app_type] => utility [patent_app_number] => 12/000434 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 7180 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721135.pdf [firstpage_image] =>[orig_patent_app_number] => 12000434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000434
Method of timing calibration using slower data rate pattern Dec 11, 2007 Issued
Array ( [id] => 4589566 [patent_doc_number] => 07861074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Electronic systems using flash memory modules as main storage and related system booting methods' [patent_app_type] => utility [patent_app_number] => 11/954411 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3987 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861074.pdf [firstpage_image] =>[orig_patent_app_number] => 11954411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954411
Electronic systems using flash memory modules as main storage and related system booting methods Dec 11, 2007 Issued
Array ( [id] => 4592073 [patent_doc_number] => 07836327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Signal processing circuit for accessing a memory based on adjustable memory control clock' [patent_app_type] => utility [patent_app_number] => 11/955192 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4436 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836327.pdf [firstpage_image] =>[orig_patent_app_number] => 11955192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955192
Signal processing circuit for accessing a memory based on adjustable memory control clock Dec 11, 2007 Issued
Array ( [id] => 4455024 [patent_doc_number] => 07966506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Saving power in a computer system' [patent_app_type] => utility [patent_app_number] => 11/955326 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966506.pdf [firstpage_image] =>[orig_patent_app_number] => 11955326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955326
Saving power in a computer system Dec 11, 2007 Issued
Array ( [id] => 8343129 [patent_doc_number] => 08245067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Power sharing among portable electronic devices' [patent_app_type] => utility [patent_app_number] => 12/158209 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3812 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12158209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/158209
Power sharing among portable electronic devices Nov 29, 2007 Issued
Array ( [id] => 7694249 [patent_doc_number] => 20080120495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'System and method of automated function activation for electronic devices' [patent_app_type] => utility [patent_app_number] => 11/984646 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4016 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20080120495.pdf [firstpage_image] =>[orig_patent_app_number] => 11984646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984646
System and method of automated function activation for electronic devices Nov 19, 2007 Issued
Array ( [id] => 4917647 [patent_doc_number] => 20080098248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Pipelined computer system with power management control' [patent_app_type] => utility [patent_app_number] => 11/931987 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3995 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098248.pdf [firstpage_image] =>[orig_patent_app_number] => 11931987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/931987
Pipelined computer system with power management control Oct 30, 2007 Issued
Menu