Search

Jafar F. Parsa

Examiner (ID: 11740, Phone: (571)272-0643 , Office: P/1671 )

Most Active Art Unit
1621
Art Unit(s)
1671, 1621, 1622, 1692
Total Applications
2798
Issued Applications
2233
Pending Applications
309
Abandoned Applications
289

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1366886 [patent_doc_number] => 06584577 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'System for measuring response time of a circuit by determining the time difference between the earlier and the later clock pulses applied to the circuit' [patent_app_type] => B1 [patent_app_number] => 09/546809 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2817 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584577.pdf [firstpage_image] =>[orig_patent_app_number] => 09546809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546809
System for measuring response time of a circuit by determining the time difference between the earlier and the later clock pulses applied to the circuit Apr 10, 2000 Issued
Array ( [id] => 1134186 [patent_doc_number] => 06792529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Common feature mode for microprocessors in a multiple microprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/547364 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4941 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792529.pdf [firstpage_image] =>[orig_patent_app_number] => 09547364 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547364
Common feature mode for microprocessors in a multiple microprocessor system Apr 10, 2000 Issued
Array ( [id] => 1214540 [patent_doc_number] => 06715091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation' [patent_app_type] => B1 [patent_app_number] => 09/546096 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1461 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715091.pdf [firstpage_image] =>[orig_patent_app_number] => 09546096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546096
System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation Apr 9, 2000 Issued
Array ( [id] => 7962193 [patent_doc_number] => 06681333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Portable computer using a stylus for power control' [patent_app_type] => B1 [patent_app_number] => 09/544207 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3467 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681333.pdf [firstpage_image] =>[orig_patent_app_number] => 09544207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/544207
Portable computer using a stylus for power control Apr 6, 2000 Issued
Array ( [id] => 1214466 [patent_doc_number] => 06715069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method and apparatus for identifying a version of an electronic assembly using a unique embedded identification signature for each different version' [patent_app_type] => B1 [patent_app_number] => 09/545359 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2607 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715069.pdf [firstpage_image] =>[orig_patent_app_number] => 09545359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545359
Method and apparatus for identifying a version of an electronic assembly using a unique embedded identification signature for each different version Apr 6, 2000 Issued
Array ( [id] => 1177779 [patent_doc_number] => 06760846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'System for determining and supplying stabilized voltage from a power supply to a data processor after a fluctuating period' [patent_app_type] => B1 [patent_app_number] => 09/545671 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9543 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760846.pdf [firstpage_image] =>[orig_patent_app_number] => 09545671 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545671
System for determining and supplying stabilized voltage from a power supply to a data processor after a fluctuating period Apr 6, 2000 Issued
Array ( [id] => 1314749 [patent_doc_number] => 06622256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof' [patent_app_type] => B1 [patent_app_number] => 09/539666 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6593 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622256.pdf [firstpage_image] =>[orig_patent_app_number] => 09539666 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539666
System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof Mar 29, 2000 Issued
Array ( [id] => 1309073 [patent_doc_number] => 06629248 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Apparatus and method for maintaining a security association for manageability across power failures' [patent_app_type] => B1 [patent_app_number] => 09/539730 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4248 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629248.pdf [firstpage_image] =>[orig_patent_app_number] => 09539730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539730
Apparatus and method for maintaining a security association for manageability across power failures Mar 29, 2000 Issued
Array ( [id] => 1319271 [patent_doc_number] => 06618814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'System for conserving power by ceasing at least one clock signal from PHY layer to MAC layer in network adapter if signal from cable is not detected' [patent_app_type] => B1 [patent_app_number] => 09/539300 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3559 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618814.pdf [firstpage_image] =>[orig_patent_app_number] => 09539300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539300
System for conserving power by ceasing at least one clock signal from PHY layer to MAC layer in network adapter if signal from cable is not detected Mar 29, 2000 Issued
Array ( [id] => 1309067 [patent_doc_number] => 06629247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Methods, systems, and computer program products for communications in uninterruptible power supply systems using controller area networks' [patent_app_type] => B1 [patent_app_number] => 09/537974 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6334 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629247.pdf [firstpage_image] =>[orig_patent_app_number] => 09537974 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537974
Methods, systems, and computer program products for communications in uninterruptible power supply systems using controller area networks Mar 27, 2000 Issued
Array ( [id] => 1250283 [patent_doc_number] => 06675307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal' [patent_app_type] => B1 [patent_app_number] => 09/536886 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4824 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675307.pdf [firstpage_image] =>[orig_patent_app_number] => 09536886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536886
Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal Mar 27, 2000 Issued
Array ( [id] => 1068376 [patent_doc_number] => 06848055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Integrated circuit having various operational modes and a method therefor' [patent_app_type] => utility [patent_app_number] => 09/535474 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3389 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848055.pdf [firstpage_image] =>[orig_patent_app_number] => 09535474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535474
Integrated circuit having various operational modes and a method therefor Mar 22, 2000 Issued
Array ( [id] => 1601905 [patent_doc_number] => 06385666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Computer system having remotely located I/O devices where signals are encoded at the computer system through two encoders and decoded at I/O devices through two decoders' [patent_app_type] => B1 [patent_app_number] => 09/524812 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7221 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385666.pdf [firstpage_image] =>[orig_patent_app_number] => 09524812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524812
Computer system having remotely located I/O devices where signals are encoded at the computer system through two encoders and decoded at I/O devices through two decoders Mar 13, 2000 Issued
Array ( [id] => 1192631 [patent_doc_number] => 06735713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter' [patent_app_type] => B1 [patent_app_number] => 09/521544 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3232 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735713.pdf [firstpage_image] =>[orig_patent_app_number] => 09521544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521544
System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter Mar 8, 2000 Issued
Array ( [id] => 4424340 [patent_doc_number] => 06266714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Audio CD play subsystem capable for playing audio CDs in a CD-ROM drive during computer system is in power-off state' [patent_app_type] => 1 [patent_app_number] => 9/514842 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5107 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266714.pdf [firstpage_image] =>[orig_patent_app_number] => 514842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514842
Audio CD play subsystem capable for playing audio CDs in a CD-ROM drive during computer system is in power-off state Feb 27, 2000 Issued
Array ( [id] => 1214259 [patent_doc_number] => 06715003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Digital camera and method for communicating digital image and at least one address image stored in the camera to a remotely located service provider' [patent_app_type] => B1 [patent_app_number] => 09/504825 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17134 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715003.pdf [firstpage_image] =>[orig_patent_app_number] => 09504825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504825
Digital camera and method for communicating digital image and at least one address image stored in the camera to a remotely located service provider Feb 13, 2000 Issued
Array ( [id] => 1206948 [patent_doc_number] => 06721884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time' [patent_app_type] => B1 [patent_app_number] => 09/501642 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721884.pdf [firstpage_image] =>[orig_patent_app_number] => 09501642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501642
System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time Feb 10, 2000 Issued
Array ( [id] => 1200883 [patent_doc_number] => 06728803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Interconnection architecture for managing multiple low bandwidth connections over a high bandwidth link' [patent_app_type] => B1 [patent_app_number] => 09/502947 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7585 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728803.pdf [firstpage_image] =>[orig_patent_app_number] => 09502947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/502947
Interconnection architecture for managing multiple low bandwidth connections over a high bandwidth link Feb 10, 2000 Issued
Array ( [id] => 1377584 [patent_doc_number] => 06578152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Dual power switching network system for isolating between different power supplies and applying appropriate power supply to a connected peripheral device' [patent_app_type] => B1 [patent_app_number] => 09/497380 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1890 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578152.pdf [firstpage_image] =>[orig_patent_app_number] => 09497380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497380
Dual power switching network system for isolating between different power supplies and applying appropriate power supply to a connected peripheral device Feb 3, 2000 Issued
Array ( [id] => 4336801 [patent_doc_number] => 06249825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Universal serial bus interface system and method' [patent_app_type] => 1 [patent_app_number] => 9/476923 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249825.pdf [firstpage_image] =>[orig_patent_app_number] => 476923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476923
Universal serial bus interface system and method Jan 3, 2000 Issued
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