
Jaison Joseph
Examiner (ID: 10639, Phone: (571)272-6041 , Office: P/2633 )
| Most Active Art Unit | 2633 |
| Art Unit(s) | 2633, 2634, 2611 |
| Total Applications | 1138 |
| Issued Applications | 927 |
| Pending Applications | 78 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18631848
[patent_doc_number] => 20230290753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-14
[patent_title] => SEMICONDUCTOR MODULE ARRAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/821579
[patent_app_country] => US
[patent_app_date] => 2022-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5448
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821579
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/821579 | Semiconductor module array device | Aug 22, 2022 | Issued |
Array
(
[id] => 18040129
[patent_doc_number] => 20220384346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => Interconnect Structure and Method of Forming Same
[patent_app_type] => utility
[patent_app_number] => 17/818414
[patent_app_country] => US
[patent_app_date] => 2022-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818414
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818414 | Interconnect structure and method of forming same | Aug 8, 2022 | Issued |
Array
(
[id] => 18959119
[patent_doc_number] => 20240047446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/882626
[patent_app_country] => US
[patent_app_date] => 2022-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6689
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882626
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/882626 | Semiconductor package and manufacturing method of the same | Aug 7, 2022 | Issued |
Array
(
[id] => 18804380
[patent_doc_number] => 11837544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-05
[patent_title] => Liner-free conductive structures with anchor points
[patent_app_type] => utility
[patent_app_number] => 17/815730
[patent_app_country] => US
[patent_app_date] => 2022-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 24
[patent_no_of_words] => 8304
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815730
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815730 | Liner-free conductive structures with anchor points | Jul 27, 2022 | Issued |
Array
(
[id] => 17993373
[patent_doc_number] => 20220359410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Semiconductor Devices and Methods of Manufacture
[patent_app_type] => utility
[patent_app_number] => 17/873387
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12599
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873387
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873387 | Semiconductor Devices and Methods of Manufacture | Jul 25, 2022 | Pending |
Array
(
[id] => 18608048
[patent_doc_number] => 11749526
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-05
[patent_title] => Semiconductor substrate and method of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 17/873122
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 34
[patent_no_of_words] => 14136
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873122
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873122 | Semiconductor substrate and method of manufacturing thereof | Jul 24, 2022 | Issued |
Array
(
[id] => 18008444
[patent_doc_number] => 20220367211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => Semiconductor Device and Methods of Manufacture
[patent_app_type] => utility
[patent_app_number] => 17/870321
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870321
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870321 | Semiconductor device comprising interconnect structures | Jul 20, 2022 | Issued |
Array
(
[id] => 18008776
[patent_doc_number] => 20220367543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => PIXEL DEVICE LAYOUT TO REDUCE PIXEL NOISE
[patent_app_type] => utility
[patent_app_number] => 17/867752
[patent_app_country] => US
[patent_app_date] => 2022-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13865
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867752
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/867752 | Pixel device layout to reduce pixel noise | Jul 18, 2022 | Issued |
Array
(
[id] => 17900787
[patent_doc_number] => 20220310449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => 3D Integrated Circuit and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 17/842392
[patent_app_country] => US
[patent_app_date] => 2022-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4204
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842392
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/842392 | 3D Integrated Circuit and Methods of Forming the Same | Jun 15, 2022 | Abandoned |
Array
(
[id] => 18097801
[patent_doc_number] => 20220416142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => HEADER FOR SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/806572
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6246
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806572
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806572 | Header for semiconductor package, and semiconductor package | Jun 12, 2022 | Issued |
Array
(
[id] => 20189829
[patent_doc_number] => 12400954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-26
[patent_title] => Semiconductor structure and method of making the same
[patent_app_type] => utility
[patent_app_number] => 17/795117
[patent_app_country] => US
[patent_app_date] => 2022-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5774
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795117
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/795117 | Semiconductor structure and method of making the same | Jun 9, 2022 | Issued |
Array
(
[id] => 18416173
[patent_doc_number] => 11670722
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Process to reduce plasma induced damage
[patent_app_type] => utility
[patent_app_number] => 17/805161
[patent_app_country] => US
[patent_app_date] => 2022-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4918
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805161
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/805161 | Process to reduce plasma induced damage | Jun 1, 2022 | Issued |
Array
(
[id] => 18814946
[patent_doc_number] => 20230389284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/804270
[patent_app_country] => US
[patent_app_date] => 2022-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 30439
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804270
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/804270 | MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES | May 25, 2022 | Pending |
Array
(
[id] => 17855421
[patent_doc_number] => 20220285464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/753000
[patent_app_country] => US
[patent_app_date] => 2022-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8216
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17753000
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/753000 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE | May 24, 2022 | Abandoned |
Array
(
[id] => 17811020
[patent_doc_number] => 20220262855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => DISPLAY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/738196
[patent_app_country] => US
[patent_app_date] => 2022-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9721
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738196
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/738196 | DISPLAY DEVICES | May 5, 2022 | Abandoned |
Array
(
[id] => 19046727
[patent_doc_number] => 11935847
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/737472
[patent_app_country] => US
[patent_app_date] => 2022-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 10600
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737472
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/737472 | Semiconductor package | May 4, 2022 | Issued |
Array
(
[id] => 19901467
[patent_doc_number] => 12279420
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => Memory having a continuous channel
[patent_app_type] => utility
[patent_app_number] => 17/723716
[patent_app_country] => US
[patent_app_date] => 2022-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 894
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723716
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/723716 | Memory having a continuous channel | Apr 18, 2022 | Issued |
Array
(
[id] => 17752841
[patent_doc_number] => 20220231046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-21
[patent_title] => Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
[patent_app_type] => utility
[patent_app_number] => 17/714924
[patent_app_country] => US
[patent_app_date] => 2022-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6767
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714924
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/714924 | Memory arrays and methods used in forming a memory array comprising strings of memory cells | Apr 5, 2022 | Issued |
Array
(
[id] => 19741190
[patent_doc_number] => 12218035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Barrier structures between external electrical connectors
[patent_app_type] => utility
[patent_app_number] => 17/712436
[patent_app_country] => US
[patent_app_date] => 2022-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4776
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712436
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/712436 | Barrier structures between external electrical connectors | Apr 3, 2022 | Issued |
Array
(
[id] => 17723471
[patent_doc_number] => 20220216193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-07
[patent_title] => SEMICONDUCTOR PACKAGE INCLUDING PROCESSOR CHIP AND MEMORY CHIP
[patent_app_type] => utility
[patent_app_number] => 17/704260
[patent_app_country] => US
[patent_app_date] => 2022-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7498
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704260
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/704260 | Semiconductor package including processor chip and memory chip | Mar 24, 2022 | Issued |