Search

James B Mullins

Examiner (ID: 7557)

Most Active Art Unit
2502
Art Unit(s)
2817, 2711, 2603, 2602, 2502, 2607, 2515, 2504, 2506
Total Applications
2038
Issued Applications
1913
Pending Applications
38
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
09/003668 MANUFACTURING METHOD FOR WAFER SLICE STARTING MATERIAL TO OPTIMIZE EXTRINSIC GETTERING DURING SEMICONDUCTOR FABRICATION Jan 6, 1998 Issued
Array ( [id] => 3990938 [patent_doc_number] => 05891771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Recessed structure for shallow trench isolation and salicide process' [patent_app_type] => 1 [patent_app_number] => 8/995339 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2097 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891771.pdf [firstpage_image] =>[orig_patent_app_number] => 995339 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995339
Recessed structure for shallow trench isolation and salicide process Dec 21, 1997 Issued
Array ( [id] => 4016851 [patent_doc_number] => 05924011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Silicide process for mixed mode product' [patent_app_type] => 1 [patent_app_number] => 8/990269 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4004 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924011.pdf [firstpage_image] =>[orig_patent_app_number] => 990269 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990269
Silicide process for mixed mode product Dec 14, 1997 Issued
Array ( [id] => 4046642 [patent_doc_number] => 05869383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'High contrast, low noise alignment mark for laser trimming of redundant memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/971667 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2792 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869383.pdf [firstpage_image] =>[orig_patent_app_number] => 971667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971667
High contrast, low noise alignment mark for laser trimming of redundant memory arrays Nov 16, 1997 Issued
Array ( [id] => 4049102 [patent_doc_number] => 05874779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film' [patent_app_type] => 1 [patent_app_number] => 8/969647 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 10120 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874779.pdf [firstpage_image] =>[orig_patent_app_number] => 969647 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969647
Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film Nov 12, 1997 Issued
Array ( [id] => 3896668 [patent_doc_number] => 05897368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method of fabricating metallized vias with steep walls' [patent_app_type] => 1 [patent_app_number] => 8/967530 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2553 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897368.pdf [firstpage_image] =>[orig_patent_app_number] => 967530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967530
Method of fabricating metallized vias with steep walls Nov 9, 1997 Issued
Array ( [id] => 4007163 [patent_doc_number] => 05888898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'HSQ baking for reduced dielectric constant' [patent_app_type] => 1 [patent_app_number] => 8/956588 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3436 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/888/05888898.pdf [firstpage_image] =>[orig_patent_app_number] => 956588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956588
HSQ baking for reduced dielectric constant Oct 22, 1997 Issued
Array ( [id] => 3991090 [patent_doc_number] => 05891782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method for fabricating an asymmetric channel doped MOS structure' [patent_app_type] => 1 [patent_app_number] => 8/918678 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5202 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891782.pdf [firstpage_image] =>[orig_patent_app_number] => 918678 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918678
Method for fabricating an asymmetric channel doped MOS structure Aug 20, 1997 Issued
Array ( [id] => 4098317 [patent_doc_number] => 06048802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines' [patent_app_type] => 1 [patent_app_number] => 8/905978 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3680 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048802.pdf [firstpage_image] =>[orig_patent_app_number] => 905978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905978
Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines Aug 4, 1997 Issued
Array ( [id] => 4050735 [patent_doc_number] => 05943591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Integrated circuit scribe line structures and methods for making same' [patent_app_type] => 1 [patent_app_number] => 8/890910 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6401 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943591.pdf [firstpage_image] =>[orig_patent_app_number] => 890910 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890910
Integrated circuit scribe line structures and methods for making same Jul 9, 1997 Issued
Array ( [id] => 3888996 [patent_doc_number] => 05834342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Self-aligned silicidation of TFT source-drain region' [patent_app_type] => 1 [patent_app_number] => 8/884917 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1678 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834342.pdf [firstpage_image] =>[orig_patent_app_number] => 884917 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884917
Self-aligned silicidation of TFT source-drain region Jun 29, 1997 Issued
Array ( [id] => 4056471 [patent_doc_number] => 05969420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor device comprising a plurality of interconnection patterns' [patent_app_type] => 1 [patent_app_number] => 8/881397 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 9991 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969420.pdf [firstpage_image] =>[orig_patent_app_number] => 881397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881397
Semiconductor device comprising a plurality of interconnection patterns Jun 23, 1997 Issued
Array ( [id] => 3886279 [patent_doc_number] => 05893755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Method of polishing a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 8/865892 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1264 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893755.pdf [firstpage_image] =>[orig_patent_app_number] => 865892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865892
Method of polishing a semiconductor wafer May 29, 1997 Issued
Array ( [id] => 4050601 [patent_doc_number] => 05943582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for forming DRAM stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 8/851115 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3483 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943582.pdf [firstpage_image] =>[orig_patent_app_number] => 851115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851115
Method for forming DRAM stacked capacitor May 4, 1997 Issued
Array ( [id] => 3999703 [patent_doc_number] => 05950102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method for fabricating air-insulated multilevel metal interconnections for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/794601 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3631 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950102.pdf [firstpage_image] =>[orig_patent_app_number] => 794601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794601
Method for fabricating air-insulated multilevel metal interconnections for integrated circuits Feb 2, 1997 Issued
Array ( [id] => 3994031 [patent_doc_number] => 05985740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of manufacturing a semiconductor device including reduction of a catalyst' [patent_app_type] => 1 [patent_app_number] => 8/783866 [patent_app_country] => US [patent_app_date] => 1997-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 11562 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985740.pdf [firstpage_image] =>[orig_patent_app_number] => 783866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783866
Method of manufacturing a semiconductor device including reduction of a catalyst Jan 15, 1997 Issued
Array ( [id] => 4062367 [patent_doc_number] => 05864175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Wrap-resistant ultra-thin integrated circuit package fabrication method' [patent_app_type] => 1 [patent_app_number] => 8/644491 [patent_app_country] => US [patent_app_date] => 1996-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5312 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864175.pdf [firstpage_image] =>[orig_patent_app_number] => 644491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644491
Wrap-resistant ultra-thin integrated circuit package fabrication method May 9, 1996 Issued
Array ( [id] => 4049137 [patent_doc_number] => 05909052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane' [patent_app_type] => 1 [patent_app_number] => 8/449722 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 73 [patent_no_of_words] => 13631 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909052.pdf [firstpage_image] =>[orig_patent_app_number] => 449722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/449722
Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane May 23, 1995 Issued
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