James B Mullins
Examiner (ID: 7557)
Most Active Art Unit | 2502 |
Art Unit(s) | 2817, 2711, 2603, 2602, 2502, 2607, 2515, 2504, 2506 |
Total Applications | 2038 |
Issued Applications | 1913 |
Pending Applications | 38 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
09/003668 | MANUFACTURING METHOD FOR WAFER SLICE STARTING MATERIAL TO OPTIMIZE EXTRINSIC GETTERING DURING SEMICONDUCTOR FABRICATION | Jan 6, 1998 | Issued |
Array
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[patent_issue_date] => 1999-04-06
[patent_title] => 'Recessed structure for shallow trench isolation and salicide process'
[patent_app_type] => 1
[patent_app_number] => 8/995339
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[patent_app_date] => 1997-12-22
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990269 | Silicide process for mixed mode product | Dec 14, 1997 | Issued |
Array
(
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[patent_issue_date] => 1999-02-09
[patent_title] => 'High contrast, low noise alignment mark for laser trimming of redundant memory arrays'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971667 | High contrast, low noise alignment mark for laser trimming of redundant memory arrays | Nov 16, 1997 | Issued |
Array
(
[id] => 4049102
[patent_doc_number] => 05874779
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[patent_issue_date] => 1999-02-23
[patent_title] => 'Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film'
[patent_app_type] => 1
[patent_app_number] => 8/969647
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Array
(
[id] => 3896668
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[patent_issue_date] => 1999-04-27
[patent_title] => 'Method of fabricating metallized vias with steep walls'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/967530 | Method of fabricating metallized vias with steep walls | Nov 9, 1997 | Issued |
Array
(
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[patent_title] => 'HSQ baking for reduced dielectric constant'
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Array
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[patent_title] => 'Method for fabricating an asymmetric channel doped MOS structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/918678 | Method for fabricating an asymmetric channel doped MOS structure | Aug 20, 1997 | Issued |
Array
(
[id] => 4098317
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[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines'
[patent_app_type] => 1
[patent_app_number] => 8/905978
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905978 | Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines | Aug 4, 1997 | Issued |
Array
(
[id] => 4050735
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[patent_title] => 'Integrated circuit scribe line structures and methods for making same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/890910 | Integrated circuit scribe line structures and methods for making same | Jul 9, 1997 | Issued |
Array
(
[id] => 3888996
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[patent_issue_date] => 1998-11-10
[patent_title] => 'Self-aligned silicidation of TFT source-drain region'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/884917 | Self-aligned silicidation of TFT source-drain region | Jun 29, 1997 | Issued |
Array
(
[id] => 4056471
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881397 | Semiconductor device comprising a plurality of interconnection patterns | Jun 23, 1997 | Issued |
Array
(
[id] => 3886279
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/865892 | Method of polishing a semiconductor wafer | May 29, 1997 | Issued |
Array
(
[id] => 4050601
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Array
(
[id] => 3999703
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Array
(
[id] => 3994031
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Array
(
[id] => 4062367
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[patent_issue_date] => 1999-01-26
[patent_title] => 'Wrap-resistant ultra-thin integrated circuit package fabrication method'
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Array
(
[id] => 4049137
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