Search

James D. Ponton

Examiner (ID: 2684, Phone: (571)272-1001 , Office: P/3763 )

Most Active Art Unit
3783
Art Unit(s)
3783, 3763
Total Applications
608
Issued Applications
438
Pending Applications
82
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18138752 [patent_doc_number] => 20230012586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SIGNAL DETECTION SYSTEM AND MEMORY DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/955670 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955670
Signal detection system for duty cycle testing and memory detection method Sep 28, 2022 Issued
Array ( [id] => 18631516 [patent_doc_number] => 20230290418 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-09-14 [patent_title] => MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETS [patent_app_type] => utility [patent_app_number] => 17/934965 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934965
Memory circuit, system and method for rapid retrieval of data sets Sep 22, 2022 Issued
Array ( [id] => 18631516 [patent_doc_number] => 20230290418 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-09-14 [patent_title] => MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETS [patent_app_type] => utility [patent_app_number] => 17/934965 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934965
Memory circuit, system and method for rapid retrieval of data sets Sep 22, 2022 Issued
Array ( [id] => 19648576 [patent_doc_number] => 20240423096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SEMICONDUCTOR DEVICE, STORAGE DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/691163 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18691163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/691163
SEMICONDUCTOR DEVICE, STORAGE DEVICE, AND ELECTRONIC DEVICE Sep 7, 2022 Pending
Array ( [id] => 19435744 [patent_doc_number] => 20240304242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Resistance Compensation Device and Method for Storage Chip, and Storage Chip [patent_app_type] => utility [patent_app_number] => 18/575264 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18575264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/575264
Resistance Compensation Device and Method for Storage Chip, and Storage Chip Sep 1, 2022 Issued
Array ( [id] => 18311876 [patent_doc_number] => 20230115776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/900228 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900228 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900228
Semiconductor memory device and test method for the same Aug 30, 2022 Issued
Array ( [id] => 19733561 [patent_doc_number] => 12211561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Semiconductor storage device acquiring voltage from dummy pillars [patent_app_type] => utility [patent_app_number] => 17/899951 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13833 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899951
Semiconductor storage device acquiring voltage from dummy pillars Aug 30, 2022 Issued
Array ( [id] => 18617719 [patent_doc_number] => 20230284460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => VARIABLE RESISTANCE NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/899898 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899898
Variable resistance non-volatile memory with a gate insulator film at a same height as a voltage application electrode Aug 30, 2022 Issued
Array ( [id] => 19610165 [patent_doc_number] => 12159040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/899974 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 35455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899974
Semiconductor memory device Aug 30, 2022 Issued
Array ( [id] => 18097038 [patent_doc_number] => 20220415379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories [patent_app_type] => utility [patent_app_number] => 17/895433 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895433
Memory system having combined high density, low bandwidth and low density, high bandwidth memories Aug 24, 2022 Issued
Array ( [id] => 18990860 [patent_doc_number] => 20240062829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/888781 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888781
Transient and stable state read operations of a memory device Aug 15, 2022 Issued
Array ( [id] => 18060596 [patent_doc_number] => 20220391682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network [patent_app_type] => utility [patent_app_number] => 17/885431 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885431
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network Aug 9, 2022 Issued
Array ( [id] => 18038871 [patent_doc_number] => 20220383087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => COMPENSATION FOR REFERENCE TRANSISTORS AND MEMORY CELLS IN ANALOG NEURO MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/885437 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885437
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network Aug 9, 2022 Issued
Array ( [id] => 18308949 [patent_doc_number] => 20230112849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => MEMORY DEVICE AND METHOD FOR DETERMINING START POINT AND END POINT OF VERIFICATION OPERATION OF TARGET STATE DURING PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/881009 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881009
Memory device and method for determining start point and end point of verification operation of target state during programming Aug 3, 2022 Issued
Array ( [id] => 20162953 [patent_doc_number] => 12389610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory device with memory strings using variable resistance memory regions [patent_app_type] => utility [patent_app_number] => 17/877714 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 78 [patent_no_of_words] => 13685 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877714
Memory device with memory strings using variable resistance memory regions Jul 28, 2022 Issued
Array ( [id] => 19093699 [patent_doc_number] => 11955163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Method and circuit for adaptive column-select line signal generation [patent_app_type] => utility [patent_app_number] => 17/875449 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8030 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875449
Method and circuit for adaptive column-select line signal generation Jul 27, 2022 Issued
Array ( [id] => 18943158 [patent_doc_number] => 20240038297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Buried Metal Techniques [patent_app_type] => utility [patent_app_number] => 17/874611 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874611
Buried metal techniques Jul 26, 2022 Issued
Array ( [id] => 18941457 [patent_doc_number] => 20240036596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => VOLTAGE REGULATION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/874867 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874867
Voltage regulation system Jul 26, 2022 Issued
Array ( [id] => 18929302 [patent_doc_number] => 20240032306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MEMORY CELLS AND ARRANGEMENTS THEREOF [patent_app_type] => utility [patent_app_number] => 17/813807 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813807
MEMORY CELLS AND ARRANGEMENTS THEREOF Jul 19, 2022 Pending
Array ( [id] => 18985520 [patent_doc_number] => 11910733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Generating self-aligned heater for PCRAM using filaments [patent_app_type] => utility [patent_app_number] => 17/813802 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813802
Generating self-aligned heater for PCRAM using filaments Jul 19, 2022 Issued
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