Search

James E. Mcdonough

Examiner (ID: 1788, Phone: (571)272-6398 , Office: P/1734 )

Most Active Art Unit
1734
Art Unit(s)
1731, 1734, 1755, 1793
Total Applications
1855
Issued Applications
1243
Pending Applications
141
Abandoned Applications
498

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20101782 [patent_doc_number] => 20250231718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => Analytics, Algorithm Architecture, and Data Processing System and Method [patent_app_type] => utility [patent_app_number] => 19/171700 [patent_app_country] => US [patent_app_date] => 2025-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19171700 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/171700
Analytics, Algorithm Architecture, and Data Processing System and Method Apr 6, 2025 Pending
Array ( [id] => 20601863 [patent_doc_number] => 20260079873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => TRANSMISSION CIRCUIT, RECEPTION CIRCUIT, TRANSMISSION AND RECEPTION CIRCUIT, AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 19/071858 [patent_app_country] => US [patent_app_date] => 2025-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19071858 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/071858
TRANSMISSION CIRCUIT, RECEPTION CIRCUIT, TRANSMISSION AND RECEPTION CIRCUIT, AND COMMUNICATION DEVICE Mar 5, 2025 Pending
Array ( [id] => 20208662 [patent_doc_number] => 20250278382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => DATA TRANSMITTING METHOD AND DATA TRANSMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 19/064777 [patent_app_country] => US [patent_app_date] => 2025-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19064777 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/064777
DATA TRANSMITTING METHOD AND DATA TRANSMITTING DEVICE Feb 26, 2025 Pending
Array ( [id] => 20619013 [patent_doc_number] => 20260089119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => Latency Tolerance Escalation Detection [patent_app_type] => utility [patent_app_number] => 19/043886 [patent_app_country] => US [patent_app_date] => 2025-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19043886 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/043886
Latency Tolerance Escalation Detection Feb 2, 2025 Pending
Array ( [id] => 20043299 [patent_doc_number] => 20250181521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => METHODS AND APPARATUS TO ESTIMATE CONSUMED MEMORY BANDWIDTH [patent_app_type] => utility [patent_app_number] => 19/043690 [patent_app_country] => US [patent_app_date] => 2025-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19043690 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/043690
METHODS AND APPARATUS TO ESTIMATE CONSUMED MEMORY BANDWIDTH Feb 2, 2025 Pending
Array ( [id] => 19963315 [patent_doc_number] => 12332816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-17 [patent_title] => Dynamic assignment of bus bandwidth for sending tensors to neural processing units [patent_app_type] => utility [patent_app_number] => 19/037189 [patent_app_country] => US [patent_app_date] => 2025-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19037189 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/037189
Dynamic assignment of bus bandwidth for sending tensors to neural processing units Jan 24, 2025 Issued
Array ( [id] => 20101966 [patent_doc_number] => 20250231902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => DATA TRANSMISSION METHOD AND APPARATUS THEREOF [patent_app_type] => utility [patent_app_number] => 19/009268 [patent_app_country] => US [patent_app_date] => 2025-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19009268 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/009268
DATA TRANSMISSION METHOD AND APPARATUS THEREOF Jan 2, 2025 Pending
Array ( [id] => 19893031 [patent_doc_number] => 20250118343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS [patent_app_type] => utility [patent_app_number] => 18/983986 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18983986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/983986
METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS Dec 16, 2024 Pending
Array ( [id] => 19848728 [patent_doc_number] => 20250094079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SMART DIMM MULTIPORT MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/969085 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18969085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/969085
SMART DIMM MULTIPORT MEMORY SYSTEM Dec 3, 2024 Pending
Array ( [id] => 19818880 [patent_doc_number] => 20250077087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => Network-Ready Storage Products for Implementations of Internet Appliances [patent_app_type] => utility [patent_app_number] => 18/954404 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954404 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954404
Network-Ready Storage Products for Implementations of Internet Appliances Nov 19, 2024 Pending
Array ( [id] => 19725704 [patent_doc_number] => 20250028455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => PROCESSORS, METHODS AND SYSTEMS TO ALLOW SECURE COMMUNICATIONS BETWEEN PROTECTED CONTAINER MEMORY AND INPUT/OUTPUT DEVICES [patent_app_type] => utility [patent_app_number] => 18/909658 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909658 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/909658
PROCESSORS, METHODS AND SYSTEMS TO ALLOW SECURE COMMUNICATIONS BETWEEN PROTECTED CONTAINER MEMORY AND INPUT/OUTPUT DEVICES Oct 7, 2024 Pending
Array ( [id] => 20716942 [patent_doc_number] => 12632192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Power safety configurations for logical address space partitions [patent_app_type] => utility [patent_app_number] => 18/890110 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18890110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/890110
Power safety configurations for logical address space partitions Sep 18, 2024 Issued
Array ( [id] => 19992496 [patent_doc_number] => 20250130718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => FLEXIBLE SUB-CHANNEL SELECTION IN A SHARED COMMUNICATION CHANNEL [patent_app_type] => utility [patent_app_number] => 18/889047 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/889047
FLEXIBLE SUB-CHANNEL SELECTION IN A SHARED COMMUNICATION CHANNEL Sep 17, 2024 Pending
Array ( [id] => 19799297 [patent_doc_number] => 20250065222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => INTERDEVICE COMMUNICATION MANAGEMENT WITHIN AN ECOSYSTEM OF ACCESSORIES [patent_app_type] => utility [patent_app_number] => 18/821162 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821162
INTERDEVICE COMMUNICATION MANAGEMENT WITHIN AN ECOSYSTEM OF ACCESSORIES Aug 29, 2024 Pending
Array ( [id] => 20570351 [patent_doc_number] => 20260064275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => TARGET DISCOVERY EXTENSION USING LOG PAGE STORAGE TAGS [patent_app_type] => utility [patent_app_number] => 18/819772 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819772 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819772
Target discovery extension using log page storage tags Aug 28, 2024 Issued
Array ( [id] => 19819253 [patent_doc_number] => 20250077460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => PCIE CLOCK DETECTION CIRCUIT AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/817233 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817233 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817233
PCIE CLOCK DETECTION CIRCUIT AND METHOD THEREOF Aug 27, 2024 Pending
Array ( [id] => 19645090 [patent_doc_number] => 20240419610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => EMBEDDED CONTROL CIRCUIT, PERIPHERAL ACCESS METHOD, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/816069 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18816069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/816069
EMBEDDED CONTROL CIRCUIT, PERIPHERAL ACCESS METHOD, AND ELECTRONIC DEVICE Aug 26, 2024 Pending
Array ( [id] => 20557117 [patent_doc_number] => 20260056903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => LINK RETENTION DURING DEVICE WARM RESET [patent_app_type] => utility [patent_app_number] => 18/815506 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815506
LINK RETENTION DURING DEVICE WARM RESET Aug 25, 2024 Pending
Array ( [id] => 19892011 [patent_doc_number] => 20250117323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => FLASH-BASED STORAGE DEVICE AND METHOD FOR FLASH MEMORY INTERCONNECTION BASED ON PACKET COMMUNICATION [patent_app_type] => utility [patent_app_number] => 18/804343 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804343 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804343
FLASH-BASED STORAGE DEVICE AND METHOD FOR FLASH MEMORY INTERCONNECTION BASED ON PACKET COMMUNICATION Aug 13, 2024 Pending
Array ( [id] => 19985761 [patent_doc_number] => 20250123983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR UPSTREAM PORT DUPLICATION ON VIRTUAL SWITCHES [patent_app_type] => utility [patent_app_number] => 18/791405 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791405
SYSTEMS, METHODS, AND APPARATUS FOR UPSTREAM PORT DUPLICATION ON VIRTUAL SWITCHES Jul 30, 2024 Pending
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