Search

James G. Moubry

Examiner (ID: 17475)

Most Active Art Unit
3747
Art Unit(s)
3747, 3783, 4179
Total Applications
1124
Issued Applications
894
Pending Applications
66
Abandoned Applications
186

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20221657 [patent_doc_number] => 20250284588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => DECODER CIRCUIT, FLASH MEMORY CONTROLLER, AND DECODING METHOD [patent_app_type] => utility [patent_app_number] => 18/950158 [patent_app_country] => US [patent_app_date] => 2024-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18950158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/950158
DECODER CIRCUIT, FLASH MEMORY CONTROLLER, AND DECODING METHOD Nov 16, 2024 Pending
Array ( [id] => 20036069 [patent_doc_number] => 20250174291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => Memory apparatus having at-speed test mechanism and memory test method of the same [patent_app_type] => utility [patent_app_number] => 18/948580 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948580
Memory apparatus having at-speed test mechanism and memory test method of the same Nov 14, 2024 Pending
Array ( [id] => 19758846 [patent_doc_number] => 20250047411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MULTI-STAGE ENCODING AND MULTI-STAGE DECODING OF INFORMATION BITS [patent_app_type] => utility [patent_app_number] => 18/927513 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/927513
MULTI-STAGE ENCODING AND MULTI-STAGE DECODING OF INFORMATION BITS Oct 24, 2024 Pending
Array ( [id] => 20652942 [patent_doc_number] => 20260104961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => HARD INFORMATION DECODER AIDED BY A SOFT INFORMATION DECODER [patent_app_type] => utility [patent_app_number] => 18/913707 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913707
HARD INFORMATION DECODER AIDED BY A SOFT INFORMATION DECODER Oct 10, 2024 Pending
Array ( [id] => 20018049 [patent_doc_number] => 20250156271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SYNDROME CALCULATION [patent_app_type] => utility [patent_app_number] => 18/913708 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913708
SYNDROME CALCULATION Oct 10, 2024 Pending
Array ( [id] => 20635737 [patent_doc_number] => 12596611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Memory system and memory management method thereof [patent_app_type] => utility [patent_app_number] => 18/802199 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/802199
Memory system and memory management method thereof Aug 12, 2024 Issued
Array ( [id] => 20070728 [patent_doc_number] => 20250208950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => MEMORY MAINTENANCE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/791126 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791126
MEMORY MAINTENANCE OPERATIONS Jul 30, 2024 Pending
Array ( [id] => 20513269 [patent_doc_number] => 20260037370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => PROBABLISTICALLY DETERMINING MEMORY PORTIONS FOR SELECT GATE SCANNING [patent_app_type] => utility [patent_app_number] => 18/790947 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790947
PROBABLISTICALLY DETERMINING MEMORY PORTIONS FOR SELECT GATE SCANNING Jul 30, 2024 Pending
Array ( [id] => 20717084 [patent_doc_number] => 12632335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Data storage system with adaptive flash media scan [patent_app_type] => utility [patent_app_number] => 18/789309 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789309
DATA STORAGE SYSTEM WITH ADAPTIVE FLASH MEDIA SCAN Jul 29, 2024 Issued
Array ( [id] => 19891977 [patent_doc_number] => 20250117289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => VALLEY CHECK MEMORY SYSTEM COMMAND [patent_app_type] => utility [patent_app_number] => 18/788550 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788550
VALLEY CHECK MEMORY SYSTEM COMMAND Jul 29, 2024 Pending
Array ( [id] => 19589413 [patent_doc_number] => 20240386970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 18/784972 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784972
METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY Jul 25, 2024 Pending
Array ( [id] => 20208610 [patent_doc_number] => 20250278330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => Low latency crosstalk mitigation in a nonvolatile memory [patent_app_type] => utility [patent_app_number] => 18/779122 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779122
Low latency crosstalk mitigation in a nonvolatile memory Jul 21, 2024 Issued
Array ( [id] => 19787341 [patent_doc_number] => 20250061020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => TRACKING LATCH UPSET EVENTS USING A TRIM REGISTER [patent_app_type] => utility [patent_app_number] => 18/778645 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778645
TRACKING LATCH UPSET EVENTS USING A TRIM REGISTER Jul 18, 2024 Pending
Array ( [id] => 19848927 [patent_doc_number] => 20250094278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => RAS TRIGGERS L2P TABLE MOVEMENT IN CXL DEVICES WITH COMPRESSION [patent_app_type] => utility [patent_app_number] => 18/778665 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778665
RAS triggers L2P table movement in CXL devices with compression Jul 18, 2024 Issued
Array ( [id] => 19558543 [patent_doc_number] => 20240370335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/778475 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778475 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778475
SEMICONDUCTOR MEMORY DEVICES Jul 18, 2024 Pending
Array ( [id] => 20717083 [patent_doc_number] => 12632334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Data transmission system, verification method and slave device [patent_app_type] => utility [patent_app_number] => 18/772297 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772297 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772297
DATA TRANSMISSION SYSTEM, VERIFICATION METHOD AND SLAVE DEVICE Jul 14, 2024 Issued
Array ( [id] => 20296028 [patent_doc_number] => 20250321271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => SYSTEM AND METHOD FOR DEVELOPING AND DEBUGGING A SILICON PRODUCTION TEST PROGRAM FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/733701 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733701
System and method for developing and debugging a silicon production test program for semiconductor devices Jun 3, 2024 Issued
Array ( [id] => 20273704 [patent_doc_number] => 12443486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Evaluation of memory device health monitoring logic [patent_app_type] => utility [patent_app_number] => 18/680470 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680470
Evaluation of memory device health monitoring logic May 30, 2024 Issued
Array ( [id] => 19605693 [patent_doc_number] => 20240396573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ASSOCIATIVE COMPUTING FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/679022 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679022
ASSOCIATIVE COMPUTING FOR ERROR CORRECTION May 29, 2024 Pending
Array ( [id] => 20365950 [patent_doc_number] => 20250355762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => Data Storage Device and Method for Generating Read Threshold Voltages [patent_app_type] => utility [patent_app_number] => 18/664514 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664514
Data Storage Device and Method for Generating Read Threshold Voltages May 14, 2024 Pending
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