Search

James G. Norman

Examiner (ID: 392, Phone: (571)270-5477 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
4175, 2827
Total Applications
794
Issued Applications
706
Pending Applications
0
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18105319 [patent_doc_number] => 11545213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Systems and methods for writing and reading data stored in a polymer using nano-channels [patent_app_type] => utility [patent_app_number] => 17/396439 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 14036 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396439
Systems and methods for writing and reading data stored in a polymer using nano-channels Aug 5, 2021 Issued
Array ( [id] => 17941512 [patent_doc_number] => 11475971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Semiconductor device and semiconductor system for testing error correction circuit [patent_app_type] => utility [patent_app_number] => 17/353423 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353423
Semiconductor device and semiconductor system for testing error correction circuit Jun 20, 2021 Issued
Array ( [id] => 17318522 [patent_doc_number] => 20210407572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => DIE VOLTAGE REGULATION [patent_app_type] => utility [patent_app_number] => 17/338458 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338458
Die voltage regulation Jun 2, 2021 Issued
Array ( [id] => 17615083 [patent_doc_number] => 20220157363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => RESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/330060 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330060
Resistive memory device May 24, 2021 Issued
Array ( [id] => 17493238 [patent_doc_number] => 11282548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-22 [patent_title] => Integrated assemblies and methods forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/307686 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4933 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307686
Integrated assemblies and methods forming integrated assemblies May 3, 2021 Issued
Array ( [id] => 17477112 [patent_doc_number] => 20220084616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => MEMORY DEVICE AND CLOCK LOCKING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/225548 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225548
Memory device and clock locking method thereof Apr 7, 2021 Issued
Array ( [id] => 18048030 [patent_doc_number] => 11521988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Three-dimensional memory device erase operation [patent_app_type] => utility [patent_app_number] => 17/214255 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214255
Three-dimensional memory device erase operation Mar 25, 2021 Issued
Array ( [id] => 17862629 [patent_doc_number] => 11443790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Spinel containing magnetic tunnel junction and method of making the same [patent_app_type] => utility [patent_app_number] => 17/192354 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192354
Spinel containing magnetic tunnel junction and method of making the same Mar 3, 2021 Issued
Array ( [id] => 17847725 [patent_doc_number] => 11437109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/188687 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 19246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/188687
Semiconductor storage device Feb 28, 2021 Issued
Array ( [id] => 17745449 [patent_doc_number] => 11393528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => RRAM circuit and method [patent_app_type] => utility [patent_app_number] => 17/179052 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179052
RRAM circuit and method Feb 17, 2021 Issued
Array ( [id] => 17302749 [patent_doc_number] => 20210398588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => SRAM STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/154608 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154608
SRAM structures Jan 20, 2021 Issued
Array ( [id] => 17757969 [patent_doc_number] => 11398267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements [patent_app_type] => utility [patent_app_number] => 17/147899 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147899
Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements Jan 12, 2021 Issued
Array ( [id] => 17737743 [patent_doc_number] => 20220223205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SETTING AN UPPER BOUND ON RRAM RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/147401 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147401
Setting an upper bound on RRAM resistance Jan 11, 2021 Issued
Array ( [id] => 17573928 [patent_doc_number] => 11322202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Semiconductor logic circuits including a non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 17/145632 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145632
Semiconductor logic circuits including a non-volatile memory cell Jan 10, 2021 Issued
Array ( [id] => 17716703 [patent_doc_number] => 11380702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Memory device having vertical structure [patent_app_type] => utility [patent_app_number] => 17/145209 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10051 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145209
Memory device having vertical structure Jan 7, 2021 Issued
Array ( [id] => 17978416 [patent_doc_number] => 11495288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method [patent_app_type] => utility [patent_app_number] => 17/143193 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9443 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143193
Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method Jan 6, 2021 Issued
Array ( [id] => 17529688 [patent_doc_number] => 11302386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Distributed bias generation for an input buffer [patent_app_type] => utility [patent_app_number] => 17/133755 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5066 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133755
Distributed bias generation for an input buffer Dec 23, 2020 Issued
Array ( [id] => 17607183 [patent_doc_number] => 11335675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Circuit-protection devices [patent_app_type] => utility [patent_app_number] => 17/128752 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 8471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128752
Circuit-protection devices Dec 20, 2020 Issued
Array ( [id] => 17389081 [patent_doc_number] => 20220036933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => MAGNETIC DEVICE INCLUDING SPIN SINKER [patent_app_type] => utility [patent_app_number] => 17/127414 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127414
Magnetic device including spin sinker Dec 17, 2020 Issued
Array ( [id] => 17772527 [patent_doc_number] => 11404479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Memory including a selector switch on a variable resistance memory cell [patent_app_type] => utility [patent_app_number] => 17/122684 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3873 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122684 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122684
Memory including a selector switch on a variable resistance memory cell Dec 14, 2020 Issued
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