
James G. Norman
Examiner (ID: 7421, Phone: (571)270-5477 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 4175, 2827 |
| Total Applications | 794 |
| Issued Applications | 706 |
| Pending Applications | 0 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16147715
[patent_doc_number] => 10706932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-07
[patent_title] => Memory device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 15/858394
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 10311
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858394
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858394 | Memory device and operating method thereof | Dec 28, 2017 | Issued |
Array
(
[id] => 15427379
[patent_doc_number] => 10546624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-28
[patent_title] => Multi-port random access memory
[patent_app_type] => utility
[patent_app_number] => 15/858398
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6000
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858398
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858398 | Multi-port random access memory | Dec 28, 2017 | Issued |
Array
(
[id] => 14541657
[patent_doc_number] => 20190206450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => TRANSMISSION LINE OPTIMIZATION FOR MULTI-DIE SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 15/858496
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21553
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858496
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858496 | Transmission line optimization for multi-die systems | Dec 28, 2017 | Issued |
Array
(
[id] => 14643965
[patent_doc_number] => 10366730
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-30
[patent_title] => Semiconductor devices and semiconductor systems including the same
[patent_app_type] => utility
[patent_app_number] => 15/816144
[patent_app_country] => US
[patent_app_date] => 2017-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816144
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/816144 | Semiconductor devices and semiconductor systems including the same | Nov 16, 2017 | Issued |
Array
(
[id] => 15014755
[patent_doc_number] => 10453533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-22
[patent_title] => Memory devices with distributed block select for a vertical string driver tile architecture
[patent_app_type] => utility
[patent_app_number] => 15/816484
[patent_app_country] => US
[patent_app_date] => 2017-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4555
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816484
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/816484 | Memory devices with distributed block select for a vertical string driver tile architecture | Nov 16, 2017 | Issued |
Array
(
[id] => 15474789
[patent_doc_number] => 10553277
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Cross point array type phase change memory device and method of driving the same
[patent_app_type] => utility
[patent_app_number] => 15/815186
[patent_app_country] => US
[patent_app_date] => 2017-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3802
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815186
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/815186 | Cross point array type phase change memory device and method of driving the same | Nov 15, 2017 | Issued |
Array
(
[id] => 15169523
[patent_doc_number] => 10490264
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-26
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/812538
[patent_app_country] => US
[patent_app_date] => 2017-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 16411
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812538
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/812538 | Semiconductor device | Nov 13, 2017 | Issued |
Array
(
[id] => 14125031
[patent_doc_number] => 10249378
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-04-02
[patent_title] => Flash memory device and method for recovering over-erased memory cells
[patent_app_type] => utility
[patent_app_number] => 15/808854
[patent_app_country] => US
[patent_app_date] => 2017-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2961
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808854
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/808854 | Flash memory device and method for recovering over-erased memory cells | Nov 8, 2017 | Issued |
Array
(
[id] => 13228407
[patent_doc_number] => 10127982
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-13
[patent_title] => Volatile memory, memory module including the same, and method for operating the memory module
[patent_app_type] => utility
[patent_app_number] => 15/730388
[patent_app_country] => US
[patent_app_date] => 2017-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5750
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730388
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/730388 | Volatile memory, memory module including the same, and method for operating the memory module | Oct 10, 2017 | Issued |
Array
(
[id] => 14300407
[patent_doc_number] => 10290334
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-14
[patent_title] => Read latency reduction in a memory device
[patent_app_type] => utility
[patent_app_number] => 15/720244
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8094
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720244
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/720244 | Read latency reduction in a memory device | Sep 28, 2017 | Issued |
Array
(
[id] => 15199849
[patent_doc_number] => 10497425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-03
[patent_title] => Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
[patent_app_type] => utility
[patent_app_number] => 15/714178
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 17152
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714178
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714178 | Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements | Sep 24, 2017 | Issued |
Array
(
[id] => 14178319
[patent_doc_number] => 10263182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-16
[patent_title] => Magnetoresistance effect element
[patent_app_type] => utility
[patent_app_number] => 15/713029
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 9419
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713029
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/713029 | Magnetoresistance effect element | Sep 21, 2017 | Issued |
Array
(
[id] => 12596538
[patent_doc_number] => 20180090676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => MAGNETORESISTANCE EFFECT ELEMENT
[patent_app_type] => utility
[patent_app_number] => 15/712661
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12309
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712661
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/712661 | Magnetoresistance effect element | Sep 21, 2017 | Issued |
Array
(
[id] => 12208326
[patent_doc_number] => 20180053552
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-22
[patent_title] => 'SEGMENTED MEMORY AND OPERATION'
[patent_app_type] => utility
[patent_app_number] => 15/690497
[patent_app_country] => US
[patent_app_date] => 2017-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8136
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690497
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/690497 | Segmented memory and operation | Aug 29, 2017 | Issued |
Array
(
[id] => 13282909
[patent_doc_number] => 10153045
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-11
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 15/688846
[patent_app_country] => US
[patent_app_date] => 2017-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11575
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688846
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/688846 | Semiconductor memory device | Aug 27, 2017 | Issued |
Array
(
[id] => 12223147
[patent_doc_number] => 20180061507
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'FUSE STATE SENSING CIRCUITS, DEVICES AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 15/687764
[patent_app_country] => US
[patent_app_date] => 2017-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 12154
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 26
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687764
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687764 | FUSE STATE SENSING CIRCUITS, DEVICES AND METHODS | Aug 27, 2017 | Abandoned |
Array
(
[id] => 12917242
[patent_doc_number] => 20180197590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/687628
[patent_app_country] => US
[patent_app_date] => 2017-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687628
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687628 | Semiconductor device for preventing read disturbance | Aug 27, 2017 | Issued |
Array
(
[id] => 12871825
[patent_doc_number] => 20180182450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => TERNARY 2-9 LINE ADDRESS DECODER REALIZED BY CNFET
[patent_app_type] => utility
[patent_app_number] => 15/687548
[patent_app_country] => US
[patent_app_date] => 2017-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5878
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 369
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687548
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687548 | Ternary 2-9 line address decoder realized by CNFET | Aug 27, 2017 | Issued |
Array
(
[id] => 13667427
[patent_doc_number] => 10163893
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-12-25
[patent_title] => Apparatus containing circuit-protection devices
[patent_app_type] => utility
[patent_app_number] => 15/687732
[patent_app_country] => US
[patent_app_date] => 2017-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 21
[patent_no_of_words] => 8366
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687732
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687732 | Apparatus containing circuit-protection devices | Aug 27, 2017 | Issued |
Array
(
[id] => 14555679
[patent_doc_number] => 10346301
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => Memory system and method for operating the same
[patent_app_type] => utility
[patent_app_number] => 15/653990
[patent_app_country] => US
[patent_app_date] => 2017-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2669
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653990
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/653990 | Memory system and method for operating the same | Jul 18, 2017 | Issued |