Search

James G. Norman

Examiner (ID: 7421, Phone: (571)270-5477 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
4175, 2827
Total Applications
794
Issued Applications
706
Pending Applications
0
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13819059 [patent_doc_number] => 10186302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Semiconductor systems performing double-write operations and methods of operating the same [patent_app_type] => utility [patent_app_number] => 15/653842 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5434 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653842
Semiconductor systems performing double-write operations and methods of operating the same Jul 18, 2017 Issued
Array ( [id] => 13257353 [patent_doc_number] => 10141374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 15/650526 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 84 [patent_no_of_words] => 26811 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650526
Memory device Jul 13, 2017 Issued
Array ( [id] => 14671547 [patent_doc_number] => 10373688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => High voltage architecture for non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/634032 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7318 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15634032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/634032
High voltage architecture for non-volatile memory Jun 26, 2017 Issued
Array ( [id] => 13470669 [patent_doc_number] => 20180286877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => NON-VOLATILE MEMORY STRUCTURE AND METHOD FOR PREVENTING NON-VOLATILE MEMORY STRUCTURE FROM GENERATING PROGRAM DISTURBANCE [patent_app_type] => utility [patent_app_number] => 15/622082 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622082 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/622082
Non-volatile memory structure and method for preventing non-volatile memory structure from generating program disturbance Jun 13, 2017 Issued
Array ( [id] => 13808155 [patent_doc_number] => 10181346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Semiconductor devices and operations thereof [patent_app_type] => utility [patent_app_number] => 15/622507 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/622507
Semiconductor devices and operations thereof Jun 13, 2017 Issued
Array ( [id] => 13694801 [patent_doc_number] => 20170358355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => CONNECTION FOR QUICK SEARCH OF REGULAR EXPRESSIONS IN DATA [patent_app_type] => utility [patent_app_number] => 15/622383 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/622383
Connection for quick search of regular expressions in data Jun 13, 2017 Issued
Array ( [id] => 13005591 [patent_doc_number] => 10026466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Staggered exit from memory power-down [patent_app_type] => utility [patent_app_number] => 15/616209 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616209
Staggered exit from memory power-down Jun 6, 2017 Issued
Array ( [id] => 12822814 [patent_doc_number] => 20180166110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/607342 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607342 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/607342
Semiconductor devices May 25, 2017 Issued
Array ( [id] => 14332601 [patent_doc_number] => 10297324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Physical secure erase of solid state drives [patent_app_type] => utility [patent_app_number] => 15/605102 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4471 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605102
Physical secure erase of solid state drives May 24, 2017 Issued
Array ( [id] => 12990256 [patent_doc_number] => 20170345828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => Non-volatile memory and method for programming and reading a memory array having the same [patent_app_type] => utility [patent_app_number] => 15/604672 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604672
Non-volatile memory and method for programming and reading a memory array having the same May 24, 2017 Issued
Array ( [id] => 11952399 [patent_doc_number] => 20170256550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SRAM Cells with Vertical Gate-All-Round MOSFETS' [patent_app_type] => utility [patent_app_number] => 15/604121 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604121
SRAM cells with vertical gate-all-round MOSFETs May 23, 2017 Issued
Array ( [id] => 13893071 [patent_doc_number] => 10199087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements [patent_app_type] => utility [patent_app_number] => 15/596812 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17129 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596812 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596812
Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements May 15, 2017 Issued
Array ( [id] => 13145947 [patent_doc_number] => 10090313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => NAND memory array with mismatched cell and bitline pitch [patent_app_type] => utility [patent_app_number] => 15/582220 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/582220
NAND memory array with mismatched cell and bitline pitch Apr 27, 2017 Issued
Array ( [id] => 11952151 [patent_doc_number] => 20170256301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'MEMORY DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/462077 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 33982 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462077 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462077
Memory device and semiconductor device Mar 16, 2017 Issued
Array ( [id] => 13098601 [patent_doc_number] => 10068643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Sense amplifier for non-volatile memory devices and related methods [patent_app_type] => utility [patent_app_number] => 15/422290 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3370 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422290 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/422290
Sense amplifier for non-volatile memory devices and related methods Jan 31, 2017 Issued
Array ( [id] => 11630614 [patent_doc_number] => 20170140803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'CONTROL SIGNAL GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/421040 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6701 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421040
Control signal generation circuit and non-volatile memory device including the same Jan 30, 2017 Issued
Array ( [id] => 11630645 [patent_doc_number] => 20170140834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'CONTROL SIGNAL GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/421009 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6701 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421009
Control signal generation circuit and non-volatile memory device including the same Jan 30, 2017 Issued
Array ( [id] => 12895504 [patent_doc_number] => 20180190343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => APPARATUS WITH LOW POWER SRAM RETENTION MODE [patent_app_type] => utility [patent_app_number] => 15/393552 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393552
Apparatus with low power SRAM retention mode Dec 28, 2016 Issued
Array ( [id] => 12691861 [patent_doc_number] => 20180122453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => OPTIMAL WRITE METHOD FOR A FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 15/391996 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391996 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391996
Optimal write method for a ferroelectric memory Dec 27, 2016 Issued
Array ( [id] => 12553458 [patent_doc_number] => 10014041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Integrated circuits, methods and interface circuitry to synchronize data transfer between high and low speed clock domains [patent_app_type] => utility [patent_app_number] => 15/389814 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389814
Integrated circuits, methods and interface circuitry to synchronize data transfer between high and low speed clock domains Dec 22, 2016 Issued
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