Search

James G. Norman

Examiner (ID: 7421, Phone: (571)270-5477 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
4175, 2827
Total Applications
794
Issued Applications
706
Pending Applications
0
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14885603 [patent_doc_number] => 10422837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Method and apparatus for estimating state of battery [patent_app_type] => utility [patent_app_number] => 15/007861 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8760 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/007861
Method and apparatus for estimating state of battery Jan 26, 2016 Issued
Array ( [id] => 12413688 [patent_doc_number] => 09971505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Memory systems including an input/output buffer circuit [patent_app_type] => utility [patent_app_number] => 14/986773 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5991 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14986773 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/986773
Memory systems including an input/output buffer circuit Jan 3, 2016 Issued
Array ( [id] => 11194123 [patent_doc_number] => 09424940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-23 [patent_title] => 'Nonvolatile memory device and method of erasing the same' [patent_app_type] => utility [patent_app_number] => 14/987178 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14987178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/987178
Nonvolatile memory device and method of erasing the same Jan 3, 2016 Issued
Array ( [id] => 11660189 [patent_doc_number] => 09673201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'SRAM cells with vertical gate-all-round MOSFETs' [patent_app_type] => utility [patent_app_number] => 14/982556 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982556 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/982556
SRAM cells with vertical gate-all-round MOSFETs Dec 28, 2015 Issued
Array ( [id] => 11904100 [patent_doc_number] => 09773539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Logical operation circuit and memory device' [patent_app_type] => utility [patent_app_number] => 14/974282 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 11910 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974282 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974282
Logical operation circuit and memory device Dec 17, 2015 Issued
Array ( [id] => 11615269 [patent_doc_number] => 09653129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Driver structure for chip-to-chip communications' [patent_app_type] => utility [patent_app_number] => 14/973530 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4277 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973530 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973530
Driver structure for chip-to-chip communications Dec 16, 2015 Issued
Array ( [id] => 11539277 [patent_doc_number] => 09613692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-04 [patent_title] => 'Sense amplifier for non-volatile memory devices and related methods' [patent_app_type] => utility [patent_app_number] => 14/971488 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971488
Sense amplifier for non-volatile memory devices and related methods Dec 15, 2015 Issued
Array ( [id] => 11385731 [patent_doc_number] => 20170011787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'DATA INPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/971266 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971266 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971266
Data input circuit and semiconductor memory device including the same Dec 15, 2015 Issued
Array ( [id] => 10983990 [patent_doc_number] => 20160180934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'APPARATUS, SYSTEMS, AND METHODS TO OPERATE A MEMORY' [patent_app_type] => utility [patent_app_number] => 14/971634 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8410 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971634 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971634
Apparatus, systems, and methods to operate a memory Dec 15, 2015 Issued
Array ( [id] => 11333524 [patent_doc_number] => 09524773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Multi-task concurrent/pipeline NAND operations on all planes' [patent_app_type] => utility [patent_app_number] => 14/966894 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 30452 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 536 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/966894
Multi-task concurrent/pipeline NAND operations on all planes Dec 10, 2015 Issued
Array ( [id] => 11227314 [patent_doc_number] => 09455040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Mitigating reliability degradation of analog memory cells during long static and erased state retention' [patent_app_type] => utility [patent_app_number] => 14/962333 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962333 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/962333
Mitigating reliability degradation of analog memory cells during long static and erased state retention Dec 7, 2015 Issued
Array ( [id] => 11651086 [patent_doc_number] => 20170146987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'ELECTRONIC CONTROL MODULE TESTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/946775 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3912 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946775
ELECTRONIC CONTROL MODULE TESTING SYSTEM Nov 19, 2015 Abandoned
Array ( [id] => 10741048 [patent_doc_number] => 20160087200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 14/947455 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3833 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947455 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/947455
Memory including a selector switch on a variable resistance memory cell Nov 19, 2015 Issued
Array ( [id] => 10772237 [patent_doc_number] => 20160118393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'NAND MEMORY ARRAY WITH MISMATCHED CELL AND BITLINE PITCH' [patent_app_type] => utility [patent_app_number] => 14/931784 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4396 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14931784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/931784
NAND memory array with mismatched cell and bitline pitch Nov 2, 2015 Issued
Array ( [id] => 10696642 [patent_doc_number] => 20160042789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'MULTIPLE LAYER FORMING SCHEME FOR VERTICAL CROSS POINT RERAM' [patent_app_type] => utility [patent_app_number] => 14/887532 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 28142 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14887532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/887532
Multiple layer forming scheme for vertical cross point reram Oct 19, 2015 Issued
Array ( [id] => 10763372 [patent_doc_number] => 20160109527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING A CHANGE IN RESISTANCE OF AN ENERGY STORAGE DEVICE AND VEHICLE' [patent_app_type] => utility [patent_app_number] => 14/882516 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6631 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882516
METHOD AND APPARATUS FOR DETERMINING A CHANGE IN RESISTANCE OF AN ENERGY STORAGE DEVICE AND VEHICLE Oct 13, 2015 Abandoned
Array ( [id] => 10764090 [patent_doc_number] => 20160110245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHOD FOR SAVING FAULT WAVE DATA' [patent_app_type] => utility [patent_app_number] => 14/882134 [patent_app_country] => US [patent_app_date] => 2015-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5010 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882134 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882134
Method for saving fault wave data Oct 12, 2015 Issued
Array ( [id] => 11556048 [patent_doc_number] => 20170102294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'Universal Sensor Interface for Machine Monitoring System' [patent_app_type] => utility [patent_app_number] => 14/880367 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2507 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14880367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/880367
Universal sensor interface for machine monitoring system Oct 11, 2015 Issued
Array ( [id] => 11802124 [patent_doc_number] => 09543016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-10 [patent_title] => 'Low power high speed program method for multi-time programmable memory device' [patent_app_type] => utility [patent_app_number] => 14/869820 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7915 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869820
Low power high speed program method for multi-time programmable memory device Sep 28, 2015 Issued
Array ( [id] => 11096266 [patent_doc_number] => 20160293235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'CONTROL SIGNAL GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/858818 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6507 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858818 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/858818
Control signal generation circuit and non-volatile memory device including the same Sep 17, 2015 Issued
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