
James G. Norman
Examiner (ID: 6663, Phone: (571)270-5477 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 4175 |
| Total Applications | 794 |
| Issued Applications | 706 |
| Pending Applications | 0 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9991179
[patent_doc_number] => 09036394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-19
[patent_title] => 'Method of driving nonvolatile semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/143544
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6077
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 608
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143544
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143544 | Method of driving nonvolatile semiconductor device | Dec 29, 2013 | Issued |
Array
(
[id] => 9900220
[patent_doc_number] => 20150055419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-26
[patent_title] => 'CONTROLLER, MEMORY SYSTEM, AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/143478
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3771
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143478
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143478 | CONTROLLER, MEMORY SYSTEM, AND METHOD | Dec 29, 2013 | Abandoned |
Array
(
[id] => 10066715
[patent_doc_number] => 09105574
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-11
[patent_title] => 'Electronic device comprising a semiconductor memory unit'
[patent_app_type] => utility
[patent_app_number] => 14/144444
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 16103
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144444
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/144444 | Electronic device comprising a semiconductor memory unit | Dec 29, 2013 | Issued |
Array
(
[id] => 9863269
[patent_doc_number] => 20150043288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CELL ARRAY'
[patent_app_type] => utility
[patent_app_number] => 14/107254
[patent_app_country] => US
[patent_app_date] => 2013-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4792
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107254
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/107254 | SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CELL ARRAY | Dec 15, 2013 | Abandoned |
Array
(
[id] => 9733293
[patent_doc_number] => 20140269002
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'TWO-TERMINAL MEMORY WITH INTRINSIC RECTIFYING CHARACTERISTIC'
[patent_app_type] => utility
[patent_app_number] => 14/108160
[patent_app_country] => US
[patent_app_date] => 2013-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 14592
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108160
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/108160 | Two-terminal memory with intrinsic rectifying characteristic | Dec 15, 2013 | Issued |
Array
(
[id] => 9915804
[patent_doc_number] => 20150071009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-12
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/106794
[patent_app_country] => US
[patent_app_date] => 2013-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6031
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106794
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/106794 | Semiconductor device | Dec 14, 2013 | Issued |
Array
(
[id] => 9900200
[patent_doc_number] => 20150055399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-26
[patent_title] => 'RESERVOIR CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/106792
[patent_app_country] => US
[patent_app_date] => 2013-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6025
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106792
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/106792 | Reservoir capacitor and semiconductor device including the same | Dec 14, 2013 | Issued |
Array
(
[id] => 9856422
[patent_doc_number] => 20150036439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-05
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/105322
[patent_app_country] => US
[patent_app_date] => 2013-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5699
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105322
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/105322 | SEMICONDUCTOR DEVICE | Dec 12, 2013 | Abandoned |
Array
(
[id] => 10966096
[patent_doc_number] => 20140369128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/106574
[patent_app_country] => US
[patent_app_date] => 2013-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6670
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106574
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/106574 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF | Dec 12, 2013 | Abandoned |
Array
(
[id] => 9544439
[patent_doc_number] => 20140169086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'COMMON SOURCE SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/105782
[patent_app_country] => US
[patent_app_date] => 2013-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9380
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105782
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/105782 | Common source semiconductor memory device | Dec 12, 2013 | Issued |
Array
(
[id] => 9655392
[patent_doc_number] => 20140226397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'NONVOLATILE MEMORY DEVICE AND CONTROL METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/104406
[patent_app_country] => US
[patent_app_date] => 2013-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104406
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/104406 | Nonvolatile memory device and control method thereof | Dec 11, 2013 | Issued |
Array
(
[id] => 9907833
[patent_doc_number] => 20150063034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-05
[patent_title] => 'MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/104270
[patent_app_country] => US
[patent_app_date] => 2013-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6075
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104270
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/104270 | Memory system including nonvolatile memory | Dec 11, 2013 | Issued |
Array
(
[id] => 10028573
[patent_doc_number] => 09070477
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-06-30
[patent_title] => 'Bit interleaved low voltage static random access memory (SRAM) and related methods'
[patent_app_type] => utility
[patent_app_number] => 14/104182
[patent_app_country] => US
[patent_app_date] => 2013-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 11245
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104182
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/104182 | Bit interleaved low voltage static random access memory (SRAM) and related methods | Dec 11, 2013 | Issued |
Array
(
[id] => 10138284
[patent_doc_number] => 09171605
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-27
[patent_title] => 'Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same'
[patent_app_type] => utility
[patent_app_number] => 14/103794
[patent_app_country] => US
[patent_app_date] => 2013-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7470
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14103794
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/103794 | Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same | Dec 10, 2013 | Issued |
Array
(
[id] => 10047156
[patent_doc_number] => 09087554
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-07-21
[patent_title] => 'Memory device, method for performing refresh operation of the memory device, and system including the same'
[patent_app_type] => utility
[patent_app_number] => 14/103402
[patent_app_country] => US
[patent_app_date] => 2013-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7320
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14103402
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/103402 | Memory device, method for performing refresh operation of the memory device, and system including the same | Dec 10, 2013 | Issued |
Array
(
[id] => 10151621
[patent_doc_number] => 09183917
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-11-10
[patent_title] => 'Memory device, operating method thereof, and system having the memory device'
[patent_app_type] => utility
[patent_app_number] => 14/103202
[patent_app_country] => US
[patent_app_date] => 2013-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 8404
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14103202
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/103202 | Memory device, operating method thereof, and system having the memory device | Dec 10, 2013 | Issued |
Array
(
[id] => 10086054
[patent_doc_number] => 09123405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-01
[patent_title] => 'Multiple device apparatus, systems, and methods'
[patent_app_type] => utility
[patent_app_number] => 14/099294
[patent_app_country] => US
[patent_app_date] => 2013-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5002
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099294
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/099294 | Multiple device apparatus, systems, and methods | Dec 5, 2013 | Issued |
Array
(
[id] => 9395269
[patent_doc_number] => 20140092675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-03
[patent_title] => 'TWO-PORT SRAM WRITE TRACKING SCHEME'
[patent_app_type] => utility
[patent_app_number] => 14/094833
[patent_app_country] => US
[patent_app_date] => 2013-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2200
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14094833
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/094833 | Two-port SRAM write tracking scheme | Dec 2, 2013 | Issued |
Array
(
[id] => 10125058
[patent_doc_number] => 09159425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'Non-volatile memory with reduced sub-threshold leakage during program and erase operations'
[patent_app_type] => utility
[patent_app_number] => 14/089016
[patent_app_country] => US
[patent_app_date] => 2013-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 4668
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089016
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/089016 | Non-volatile memory with reduced sub-threshold leakage during program and erase operations | Nov 24, 2013 | Issued |
Array
(
[id] => 10253868
[patent_doc_number] => 20150138864
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES'
[patent_app_type] => utility
[patent_app_number] => 14/086248
[patent_app_country] => US
[patent_app_date] => 2013-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2317
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086248
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/086248 | MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES | Nov 20, 2013 | Abandoned |