Search

James G. Norman

Examiner (ID: 15088, Phone: (571)270-5477 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
4175, 2827
Total Applications
794
Issued Applications
706
Pending Applications
0
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8813311 [patent_doc_number] => 20130114356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS, AND DIVISIONAL PROGRAM CONTROL CIRCUIT AND PROGRAM METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/445196 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9962 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445196
Semiconductor memory apparatus, and divisional program control circuit and program method therefor Apr 11, 2012 Issued
Array ( [id] => 9067002 [patent_doc_number] => 20130258758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'Single Cycle Data Copy for Two-Port SRAM' [patent_app_type] => utility [patent_app_number] => 13/435828 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6775 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435828
Single cycle data copy for two-port SRAM Mar 29, 2012 Issued
Array ( [id] => 8714684 [patent_doc_number] => 08400828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/435901 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 92 [patent_no_of_words] => 40380 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435901 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435901
Nonvolatile semiconductor memory device Mar 29, 2012 Issued
Array ( [id] => 10871847 [patent_doc_number] => 08897060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Magnetoresistance effect element and magnetic memory' [patent_app_type] => utility [patent_app_number] => 13/432626 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6634 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432626 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432626
Magnetoresistance effect element and magnetic memory Mar 27, 2012 Issued
Array ( [id] => 9997569 [patent_doc_number] => 09042180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Charge pump redundancy in a memory' [patent_app_type] => utility [patent_app_number] => 13/995166 [patent_app_country] => US [patent_app_date] => 2012-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7994 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995166 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995166
Charge pump redundancy in a memory Mar 24, 2012 Issued
Array ( [id] => 9021885 [patent_doc_number] => 08531875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Magnetic memory' [patent_app_type] => utility [patent_app_number] => 13/426139 [patent_app_country] => US [patent_app_date] => 2012-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 9294 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13426139 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/426139
Magnetic memory Mar 20, 2012 Issued
Array ( [id] => 9200460 [patent_doc_number] => 20130339775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'POWER-MANAGEMENT FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/980368 [patent_app_country] => US [patent_app_date] => 2012-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8179 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980368 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980368
Power-management for integrated circuits Mar 7, 2012 Issued
Array ( [id] => 8263645 [patent_doc_number] => 20120163065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Spatial Correlation of Reference Cells in Resistive Memory Array' [patent_app_type] => utility [patent_app_number] => 13/410783 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/410783
Spatial correlation of reference cells in resistive memory array Mar 1, 2012 Issued
Array ( [id] => 8311805 [patent_doc_number] => 20120188826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS' [patent_app_type] => utility [patent_app_number] => 13/407660 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14069 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407660 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407660
Memory architecture having two independently controlled voltage pumps Feb 27, 2012 Issued
Array ( [id] => 8238930 [patent_doc_number] => 20120147665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells' [patent_app_type] => utility [patent_app_number] => 13/400515 [patent_app_country] => US [patent_app_date] => 2012-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13400515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/400515
Predictive thermal preconditioning and timing control for non-volatile memory cells Feb 19, 2012 Issued
Array ( [id] => 8238957 [patent_doc_number] => 20120147691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/398495 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13032 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13398495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/398495
Semiconductor storage device and memory system Feb 15, 2012 Issued
Array ( [id] => 9172982 [patent_doc_number] => 20130314968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY' [patent_app_type] => utility [patent_app_number] => 13/983998 [patent_app_country] => US [patent_app_date] => 2012-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3751 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13983998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/983998
Offsetting clock package pins in a clamshell topology to improve signal integrity Feb 6, 2012 Issued
Array ( [id] => 9678639 [patent_doc_number] => 08817559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/364017 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 49 [patent_no_of_words] => 27517 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364017
Semiconductor device and manufacturing method thereof Jan 31, 2012 Issued
Array ( [id] => 10889411 [patent_doc_number] => 08913413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Memory system with sectional data lines' [patent_app_type] => utility [patent_app_number] => 13/362311 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362311 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362311
Memory system with sectional data lines Jan 30, 2012 Issued
Array ( [id] => 9924622 [patent_doc_number] => 08982597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Memory system with sectional data lines' [patent_app_type] => utility [patent_app_number] => 13/362320 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9210 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362320
Memory system with sectional data lines Jan 30, 2012 Issued
Array ( [id] => 8195358 [patent_doc_number] => 20120120736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Self Pre-Charging and Equalizing Bit Line Sense Amplifier' [patent_app_type] => utility [patent_app_number] => 13/357938 [patent_app_country] => US [patent_app_date] => 2012-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120736.pdf [firstpage_image] =>[orig_patent_app_number] => 13357938 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357938
Self pre-charging and equalizing bit line sense amplifier Jan 24, 2012 Issued
Array ( [id] => 10899858 [patent_doc_number] => 08923087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Method and apparatus for decreasing leakage power consumption in power gated memories' [patent_app_type] => utility [patent_app_number] => 13/354222 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6781 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13354222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/354222
Method and apparatus for decreasing leakage power consumption in power gated memories Jan 18, 2012 Issued
Array ( [id] => 8195319 [patent_doc_number] => 20120120701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/350823 [patent_app_country] => US [patent_app_date] => 2012-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6007 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120701.pdf [firstpage_image] =>[orig_patent_app_number] => 13350823 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/350823
TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES Jan 15, 2012 Abandoned
Array ( [id] => 8300272 [patent_doc_number] => 20120182816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/350640 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 29569 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13350640 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/350640
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jan 12, 2012 Abandoned
Array ( [id] => 8311817 [patent_doc_number] => 20120188814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'MEMORY DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/350086 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 33924 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13350086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/350086
Memory device and semiconductor device Jan 12, 2012 Issued
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