Search

James G. Norman

Examiner (ID: 6052, Phone: (571)270-5477 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 4175
Total Applications
794
Issued Applications
706
Pending Applications
0
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17203256 [patent_doc_number] => 20210343351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => DEFECT DETECTION DURING PROGRAM VERIFY IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 15/929439 [patent_app_country] => US [patent_app_date] => 2020-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929439
Defect detection during program verify in a memory sub-system Apr 30, 2020 Issued
Array ( [id] => 16241341 [patent_doc_number] => 20200258575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/862380 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862380
Memory devices with distributed block select for a vertical string driver tile architecture Apr 28, 2020 Issued
Array ( [id] => 17107257 [patent_doc_number] => 11127482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Detection circuitry to detect a deck of a memory array [patent_app_type] => utility [patent_app_number] => 16/847181 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847181 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847181
Detection circuitry to detect a deck of a memory array Apr 12, 2020 Issued
Array ( [id] => 16210150 [patent_doc_number] => 20200243140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/846539 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846539
Nonvolatile memory device and storage device including nonvolatile memory device Apr 12, 2020 Issued
Array ( [id] => 16192897 [patent_doc_number] => 20200233746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY [patent_app_type] => utility [patent_app_number] => 16/844925 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844925
Systems, methods, and apparatuses for stacked memory Apr 8, 2020 Issued
Array ( [id] => 17077739 [patent_doc_number] => 11114150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Memory system with multiple open rows per bank [patent_app_type] => utility [patent_app_number] => 16/838646 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838646
Memory system with multiple open rows per bank Apr 1, 2020 Issued
Array ( [id] => 16180156 [patent_doc_number] => 20200227125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => BIT LINE VOLTAGE CONTROL FOR DAMPING MEMORY PROGRAMMING [patent_app_type] => utility [patent_app_number] => 16/829692 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829692
Bit line voltage control for damping memory programming Mar 24, 2020 Issued
Array ( [id] => 16566641 [patent_doc_number] => 10892015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Nonvolatile memory device and method of programming in the same [patent_app_type] => utility [patent_app_number] => 16/822905 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/822905
Nonvolatile memory device and method of programming in the same Mar 17, 2020 Issued
Array ( [id] => 16163125 [patent_doc_number] => 20200219795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Integrated Assemblies Comprising Redundant Wiring Routes, and Integrated Circuit Decks Having Openings Extending Therethrough [patent_app_type] => utility [patent_app_number] => 16/821841 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821841 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821841
Integrated assemblies comprising redundant wiring routes, and integrated circuit decks having openings extending therethrough Mar 16, 2020 Issued
Array ( [id] => 17098951 [patent_doc_number] => 20210286742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => Single Command for Reading then Clearing a Memory Buffer [patent_app_type] => utility [patent_app_number] => 16/818793 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818793 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818793
Single command for reading then clearing a memory buffer Mar 12, 2020 Issued
Array ( [id] => 16759578 [patent_doc_number] => 10978133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Memory device and memory system comprising the same [patent_app_type] => utility [patent_app_number] => 16/813962 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 7321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813962
Memory device and memory system comprising the same Mar 9, 2020 Issued
Array ( [id] => 16286004 [patent_doc_number] => 20200279606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => RESISTIVE MEMORY [patent_app_type] => utility [patent_app_number] => 16/801878 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801878
Resistive memory Feb 25, 2020 Issued
Array ( [id] => 16691857 [patent_doc_number] => 20210074336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => MEMORY SYSTEM AND POWER SUPPLY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/802496 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802496
MEMORY SYSTEM AND POWER SUPPLY CIRCUIT Feb 25, 2020 Abandoned
Array ( [id] => 16272038 [patent_doc_number] => 20200273526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => METHOD AND SEMICONDUCTOR DEVICE FOR PROTECTING A SEMICONDUCTOR INTEGRATED CIRCUIT FROM REVERSE ENGINEERING [patent_app_type] => utility [patent_app_number] => 16/800369 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800369
Method and semiconductor device for protecting a semiconductor integrated circuit from reverse engineering Feb 24, 2020 Issued
Array ( [id] => 16636627 [patent_doc_number] => 10915133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Non-dominant pole tracking compensation for large dynamic current and capacitive load reference generator [patent_app_type] => utility [patent_app_number] => 16/800260 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 12944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800260
Non-dominant pole tracking compensation for large dynamic current and capacitive load reference generator Feb 24, 2020 Issued
Array ( [id] => 16080137 [patent_doc_number] => 20200194055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => APPARATUSES AND METHODS FOR SWITCHING REFRESH STATE IN A MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/796696 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796696 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796696
Apparatuses and methods for switching refresh state in a memory circuit Feb 19, 2020 Issued
Array ( [id] => 16973763 [patent_doc_number] => 11069745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/787225 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 84 [patent_no_of_words] => 26823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787225
Memory device Feb 10, 2020 Issued
Array ( [id] => 17025544 [patent_doc_number] => 20210249416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Integrated Assemblies having Voltage Sources Coupled to Shields and/or Plate Electrodes through Capacitors [patent_app_type] => utility [patent_app_number] => 16/785942 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785942 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785942
Integrated assemblies having voltage sources coupled to shields and/or plate electrodes through capacitors Feb 9, 2020 Issued
Array ( [id] => 16000345 [patent_doc_number] => 20200176043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, MAGNETORESISTANCE EFFECT ELEMENT, AND MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/785987 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785987
Spin current magnetization rotational element, magnetoresistance effect element, and magnetic memory Feb 9, 2020 Issued
Array ( [id] => 17009445 [patent_doc_number] => 20210240606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => METHOD AND APPARATUS FOR ELIMINATING BIT DISTURBANCE ERRORS IN NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/782139 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782139
Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices Feb 4, 2020 Issued
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