Search

James J. Lee

Examiner (ID: 10231, Phone: (571)270-5965 , Office: P/2195 )

Most Active Art Unit
2195
Art Unit(s)
2195, 3668
Total Applications
306
Issued Applications
247
Pending Applications
3
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17917186 [patent_doc_number] => 20220319582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING MEMORY MANAGEMENT PROGRAM [patent_app_type] => utility [patent_app_number] => 17/582039 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582039
MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING MEMORY MANAGEMENT PROGRAM Jan 23, 2022 Abandoned
Array ( [id] => 19316023 [patent_doc_number] => 12041860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Resistive memory device and method for manufacturing with protrusion of electrode [patent_app_type] => utility [patent_app_number] => 17/581153 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581153
Resistive memory device and method for manufacturing with protrusion of electrode Jan 20, 2022 Issued
Array ( [id] => 19414501 [patent_doc_number] => 12080333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Semiconductor system for performing an active operation using an active period control method [patent_app_type] => utility [patent_app_number] => 17/577289 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13943 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577289
Semiconductor system for performing an active operation using an active period control method Jan 16, 2022 Issued
Array ( [id] => 19426597 [patent_doc_number] => 12086015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Low power state implementation in a power management circuit [patent_app_type] => utility [patent_app_number] => 17/575334 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575334 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575334
Low power state implementation in a power management circuit Jan 12, 2022 Issued
Array ( [id] => 19229414 [patent_doc_number] => 12009055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Far end driver for memory clock [patent_app_type] => utility [patent_app_number] => 17/571670 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571670
Far end driver for memory clock Jan 9, 2022 Issued
Array ( [id] => 18299132 [patent_doc_number] => 20230108818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SEMICONDUCTOR SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/646439 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646439
Semiconductor system and operating method to adjust temperature of semiconductor apparatus and control device Dec 28, 2021 Issued
Array ( [id] => 19016078 [patent_doc_number] => 11923018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Semiconductor memory device and method with multiple verify voltages [patent_app_type] => utility [patent_app_number] => 17/561172 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 13125 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561172
Semiconductor memory device and method with multiple verify voltages Dec 22, 2021 Issued
Array ( [id] => 19029003 [patent_doc_number] => 11928362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Fuse latch of semiconductor device for latching data of a repair fuse cell [patent_app_type] => utility [patent_app_number] => 17/557009 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4755 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557009
Fuse latch of semiconductor device for latching data of a repair fuse cell Dec 19, 2021 Issued
Array ( [id] => 17778513 [patent_doc_number] => 20220244863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => TECHNIQUES FOR PERFORMING WRITE TRAINING ON A DYNAMIC RANDOM-ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/550811 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550811
Techniques for performing write training on a dynamic random-access memory Dec 13, 2021 Issued
Array ( [id] => 17508796 [patent_doc_number] => 20220101899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DECODE CIRCUITRY COUPLED TO A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/550668 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550668
Decode circuitry coupled to a memory array Dec 13, 2021 Issued
Array ( [id] => 17508828 [patent_doc_number] => 20220101931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MEMORY DEVICE INCLUDING MASSBIT COUNTER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/548774 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548774 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548774
Memory device including massbit counter and method of operating the same Dec 12, 2021 Issued
Array ( [id] => 19029760 [patent_doc_number] => 11929123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Semiconductor memory device with erase loops [patent_app_type] => utility [patent_app_number] => 17/643726 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 13288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643726
Semiconductor memory device with erase loops Dec 9, 2021 Issued
Array ( [id] => 18426177 [patent_doc_number] => 20230180642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => CROSSBAR MEMORY ARRAY IN FRONT END OF LINE [patent_app_type] => utility [patent_app_number] => 17/457926 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457926
Crossbar memory array in front end of line Dec 6, 2021 Issued
Array ( [id] => 17551323 [patent_doc_number] => 20220122665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => MEMORY DEVICES FOR PATTERN MATCHING [patent_app_type] => utility [patent_app_number] => 17/542562 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542562
Memory devices for pattern matching based on majority of cell pair match Dec 5, 2021 Issued
Array ( [id] => 17599066 [patent_doc_number] => 20220148640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => APPARATUSES AND METHODS FOR A MULTI-BIT DUTY CYCLE MONITOR [patent_app_type] => utility [patent_app_number] => 17/455468 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455468
Apparatuses and methods for a multi-bit duty cycle monitor Nov 17, 2021 Issued
Array ( [id] => 17779833 [patent_doc_number] => 20220246183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => TECHNIQUES FOR PERFORMING COMMAND ADDRESS INTERFACE TRAINING ON A DYNAMIC RANDOM-ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/523778 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523778
Techniques for performing command address in interface training on a dynamic random-access memory Nov 9, 2021 Issued
Array ( [id] => 17779834 [patent_doc_number] => 20220246184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => TECHNIQUES FOR PERFORMING WRITE TRAINING ON A DYNAMIC RANDOM-ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/523779 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523779
Techniques for performing write training on a dynamic random-access memory Nov 9, 2021 Issued
Array ( [id] => 17431439 [patent_doc_number] => 20220059148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/518888 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518888
Memory device for supporting command bus training mode and method of operating the same Nov 3, 2021 Issued
Array ( [id] => 18721248 [patent_doc_number] => 11798600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Read accelerator circuit [patent_app_type] => utility [patent_app_number] => 17/518486 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3292 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518486
Read accelerator circuit Nov 2, 2021 Issued
Array ( [id] => 19046466 [patent_doc_number] => 11935585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Pseudo multi-plane read methods and apparatus for non-volatile memory devices [patent_app_type] => utility [patent_app_number] => 17/509725 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509725
Pseudo multi-plane read methods and apparatus for non-volatile memory devices Oct 24, 2021 Issued
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