Search

James J. Lee

Examiner (ID: 10231, Phone: (571)270-5965 , Office: P/2195 )

Most Active Art Unit
2195
Art Unit(s)
2195, 3668
Total Applications
306
Issued Applications
247
Pending Applications
3
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19355521 [patent_doc_number] => 12055962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Low-voltage power supply reference generator circuit [patent_app_type] => utility [patent_app_number] => 17/508016 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508016
Low-voltage power supply reference generator circuit Oct 21, 2021 Issued
Array ( [id] => 18520617 [patent_doc_number] => 11710511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor device having a high-speed memory with stable operation [patent_app_type] => utility [patent_app_number] => 17/501411 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8801 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501411
Semiconductor device having a high-speed memory with stable operation Oct 13, 2021 Issued
Array ( [id] => 18219348 [patent_doc_number] => 11594294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Memory device including massbit counter and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/493063 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 15467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493063
Memory device including massbit counter and method of operating the same Oct 3, 2021 Issued
Array ( [id] => 18414905 [patent_doc_number] => 11669447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Modifying subsets of memory bank operating parameters [patent_app_type] => utility [patent_app_number] => 17/488190 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 20662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488190
Modifying subsets of memory bank operating parameters Sep 27, 2021 Issued
Array ( [id] => 18317359 [patent_doc_number] => 11631443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Semiconductor device and electronic device with serial, data transfer mechanism [patent_app_type] => utility [patent_app_number] => 17/480359 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480359
Semiconductor device and electronic device with serial, data transfer mechanism Sep 20, 2021 Issued
Array ( [id] => 18935217 [patent_doc_number] => 11887655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches [patent_app_type] => utility [patent_app_number] => 17/474172 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474172
Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches Sep 13, 2021 Issued
Array ( [id] => 17522051 [patent_doc_number] => 20220107900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => ERROR CACHE SYSTEM WITH COARSE AND FINE SEGMENTS FOR POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 17/473880 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 61366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473880
Error cache system with coarse and fine segments for power optimization Sep 12, 2021 Issued
Array ( [id] => 17522039 [patent_doc_number] => 20220107888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => HEURISTICS FOR SELECTING SUBSEGMENTS FOR ENTRY IN AND ENTRY OUT OPERATIONS IN AN ERROR CACHE SYSTEM WITH COARSE AND FINE GRAIN SEGMENTS [patent_app_type] => utility [patent_app_number] => 17/473924 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 61377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473924
Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Sep 12, 2021 Issued
Array ( [id] => 18242365 [patent_doc_number] => 20230074676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => COMPACT MRAM ARCHITECTURE WITH MAGNETIC BOTTOM ELECTRODE [patent_app_type] => utility [patent_app_number] => 17/469350 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469350
Compact MRAM architecture with magnetic bottom electrode Sep 7, 2021 Issued
Array ( [id] => 17978426 [patent_doc_number] => 11495298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Three dimension memory device and ternary content addressable memory cell thereof [patent_app_type] => utility [patent_app_number] => 17/465651 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3950 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465651
Three dimension memory device and ternary content addressable memory cell thereof Sep 1, 2021 Issued
Array ( [id] => 18721262 [patent_doc_number] => 11798614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Automated voltage demarcation (VDM) adjustment for memory device [patent_app_type] => utility [patent_app_number] => 17/463274 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463274
Automated voltage demarcation (VDM) adjustment for memory device Aug 30, 2021 Issued
Array ( [id] => 17295231 [patent_doc_number] => 20210391070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SYSTEM AND METHOD FOR COORDINATED MOTION AMONG HETEROGENEOUS DEVICES USING A MOVEMENT TOKEN [patent_app_type] => utility [patent_app_number] => 17/412812 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412812
System and method for coordinated motion among heterogeneous devices using a movement token Aug 25, 2021 Issued
Array ( [id] => 18480990 [patent_doc_number] => 11694741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Internal voltage generation circuit and semiconductor memory apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/411699 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411699
Internal voltage generation circuit and semiconductor memory apparatus including the same Aug 24, 2021 Issued
Array ( [id] => 17277665 [patent_doc_number] => 20210383863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMING WITH CAPABILITY OF DETECTING SUDDEN POWER OFF [patent_app_type] => utility [patent_app_number] => 17/408414 [patent_app_country] => US [patent_app_date] => 2021-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408414
Nonvolatile memory device and method of programing with capability of detecting sudden power off Aug 20, 2021 Issued
Array ( [id] => 17462259 [patent_doc_number] => 20220075564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY DEVICE FOR ADJUSTING DELAY ON DATA CLOCK PATH, MEMORY SYSTEM INCLUDING THE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/405753 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405753 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405753
Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system Aug 17, 2021 Issued
Array ( [id] => 17416806 [patent_doc_number] => 20220051710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => MEMORY DEVICE WHICH GENERATES IMPROVED WRITE VOLTAGE ACCORDING TO SIZE OF MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/399264 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399264
Memory device which generates improved write voltage according to size of memory cell Aug 10, 2021 Issued
Array ( [id] => 18548048 [patent_doc_number] => 11721406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Generating test data for a memory system design based on operation of a test system, and related methods, devices, and systems [patent_app_type] => utility [patent_app_number] => 17/395988 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395988 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395988
Generating test data for a memory system design based on operation of a test system, and related methods, devices, and systems Aug 5, 2021 Issued
Array ( [id] => 18623544 [patent_doc_number] => 11756597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Power-on read demarcation voltage optimization [patent_app_type] => utility [patent_app_number] => 17/393112 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393112 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393112
Power-on read demarcation voltage optimization Aug 2, 2021 Issued
Array ( [id] => 17463422 [patent_doc_number] => 20220076728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY APPARATUS AND INITIALIZATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/393383 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393383
Memory apparatus and initialization method with short burst type refresh operation Aug 2, 2021 Issued
Array ( [id] => 17359650 [patent_doc_number] => 20220020446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => LEAKAGE SOURCE DETECTION [patent_app_type] => utility [patent_app_number] => 17/387290 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387290
Leakage source detection for memory with varying conductive path lengths Jul 27, 2021 Issued
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