Search

James J. Lee

Examiner (ID: 10231, Phone: (571)270-5965 , Office: P/2195 )

Most Active Art Unit
2195
Art Unit(s)
2195, 3668
Total Applications
306
Issued Applications
247
Pending Applications
3
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17723175 [patent_doc_number] => 20220215897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN [patent_app_type] => utility [patent_app_number] => 17/141176 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141176
Method and memory device with increased read and write margin Jan 3, 2021 Issued
Array ( [id] => 17757962 [patent_doc_number] => 11398260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Network device and network connection method with linear feedback shift register [patent_app_type] => utility [patent_app_number] => 17/138975 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4932 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138975
Network device and network connection method with linear feedback shift register Dec 30, 2020 Issued
Array ( [id] => 17971104 [patent_doc_number] => 11488651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Systems and methods for improving power efficiency in refreshing memory banks [patent_app_type] => utility [patent_app_number] => 17/135403 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5087 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135403
Systems and methods for improving power efficiency in refreshing memory banks Dec 27, 2020 Issued
Array ( [id] => 16765288 [patent_doc_number] => 20210110870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => TECHNIQUES FOR INITIALIZING RESISTIVE MEMORY DEVICES BY APPLYING DIFFERENT POLARITY VOLTAGES ACROSS RESISTANCE CHANGE MATERIAL [patent_app_type] => utility [patent_app_number] => 17/128707 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128707
Techniques for initializing resistive memory devices by applying voltages with different polarities Dec 20, 2020 Issued
Array ( [id] => 18712562 [patent_doc_number] => 20230335195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => MEMORY PACKAGE CHIP AND SIGNAL PROCESSING MEHTHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/025399 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025399
Memory packaged chip and signal processing method therefor Dec 15, 2020 Issued
Array ( [id] => 16722308 [patent_doc_number] => 20210089455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => CIRCUIT ENGINE FOR MANAGING MEMORY META-STABILITY [patent_app_type] => utility [patent_app_number] => 17/111207 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111207 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111207
Circuit engine for managing memory meta-stability Dec 2, 2020 Issued
Array ( [id] => 16752264 [patent_doc_number] => 20210104276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => NEURAL NETWORK MEMORY [patent_app_type] => utility [patent_app_number] => 17/104547 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104547
Neural network memory with mechanism to change synaptic weight Nov 24, 2020 Issued
Array ( [id] => 19213466 [patent_doc_number] => 12002538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Memory device with data mergers and aligner [patent_app_type] => utility [patent_app_number] => 17/777010 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 7281 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17777010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/777010
Memory device with data mergers and aligner Nov 16, 2020 Issued
Array ( [id] => 16887365 [patent_doc_number] => 20210173562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => RESET VERIFICATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/097766 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097766
Reset verification in a memory system by using a mode register Nov 12, 2020 Issued
Array ( [id] => 16677041 [patent_doc_number] => 20210065807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => I/O BUFFER OFFSET MITIGATION [patent_app_type] => utility [patent_app_number] => 17/096055 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096055
I/O buffer offset mitigation while applying a same voltage level to two inputs of an input buffer Nov 11, 2020 Issued
Array ( [id] => 16692385 [patent_doc_number] => 20210074864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => ELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/087842 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087842
Electronic devices including capacitors with multiple dielectric materials, and related systems Nov 2, 2020 Issued
Array ( [id] => 17668111 [patent_doc_number] => 11361814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Column selector architecture with edge mat optimization [patent_app_type] => utility [patent_app_number] => 17/084250 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084250
Column selector architecture with edge mat optimization Oct 28, 2020 Issued
Array ( [id] => 16616977 [patent_doc_number] => 20210035630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => PROGRAMMING MEMORY CELLS OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/074690 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074690
Programming memory cells where higher levels are programmed prior to lower levels Oct 19, 2020 Issued
Array ( [id] => 17424093 [patent_doc_number] => 11257554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Semiconductor memory device and method with selection transistor programming and verification mechanism [patent_app_type] => utility [patent_app_number] => 17/069953 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069953
Semiconductor memory device and method with selection transistor programming and verification mechanism Oct 13, 2020 Issued
Array ( [id] => 16587847 [patent_doc_number] => 20210022249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => MEMORY SYSTEM AND STORAGE DEVICE INCLUDING PRINTED CIRCUIT BOARD WHERE CHANNEL GROUPS HAVE BOTH POINT TO POINT TOPOLOGY AND DAISY CHAIN TOPOLOGY [patent_app_type] => utility [patent_app_number] => 17/060833 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060833
Memory system and storage device including printed circuit board with subset of channels arranged in point-to-point topology and subset of channels arranged in daisy-chain topology Sep 30, 2020 Issued
Array ( [id] => 17516632 [patent_doc_number] => 11295791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => SRAM with local bit line, input/output circuit, and global bit line [patent_app_type] => utility [patent_app_number] => 17/027209 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027209
SRAM with local bit line, input/output circuit, and global bit line Sep 20, 2020 Issued
Array ( [id] => 16560123 [patent_doc_number] => 20210005272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/024370 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024370
Semiconductor memory device including a first electrode to input command set and output read data and a second electrode to supply power Sep 16, 2020 Issued
Array ( [id] => 17500460 [patent_doc_number] => 11289170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Nonvolatile memory device with capability of determing degradation of data erase characteristics [patent_app_type] => utility [patent_app_number] => 17/021407 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 15310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021407
Nonvolatile memory device with capability of determing degradation of data erase characteristics Sep 14, 2020 Issued
Array ( [id] => 17668567 [patent_doc_number] => 11362272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Resistive memory device and reliability enhancement method thereof by using ratio of set current and reference current [patent_app_type] => utility [patent_app_number] => 17/002759 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3756 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002759
Resistive memory device and reliability enhancement method thereof by using ratio of set current and reference current Aug 24, 2020 Issued
Array ( [id] => 18585726 [patent_doc_number] => 20230267990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SYMMETRIC MEMORY CELL AND BNN CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/005101 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/005101
Symmetric memory cell and BNN circuit Aug 23, 2020 Issued
Menu