
James J. Seidleck
Supervisory Patent Examiner (ID: 17261, Phone: (571)272-1078 , Office: P/1765 )
| Most Active Art Unit | 1508 |
| Art Unit(s) | 1506, 1508, 1512, 1796, 1502, 2401, 1765, 1711, 1507 |
| Total Applications | 858 |
| Issued Applications | 628 |
| Pending Applications | 34 |
| Abandoned Applications | 197 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 7548055
[patent_doc_number] => 08056036
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[patent_title] => 'Semiconductor integrated circuit and method of designing thereof based on TPI'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/153596 | Semiconductor integrated circuit and method of designing thereof based on TPI | May 20, 2008 | Issued |
Array
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[patent_doc_number] => 20090141566
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[patent_issue_date] => 2009-06-04
[patent_title] => 'STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/110456 | Structure for implementing memory array device with built in computation capability | Apr 27, 2008 | Issued |
Array
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[patent_title] => 'ROUTING CHANNEL DISPLAYING METHOD AND COMPUTER-ACCESSIBLE STORAGE MEDIUM THEREOF'
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[patent_title] => 'Performance Visualization of Delay in Circuit Design'
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[patent_title] => 'Methods of implementing multi-cycle paths in electronic circuits'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/037664 | RELIABILITY DESIGN METHOD | Feb 25, 2008 | Abandoned |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/034644 | Computer program product, apparatus, and method for inserting components in a hierarchical chip design | Feb 19, 2008 | Issued |
Array
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[patent_title] => 'Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC)'
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Array
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Array
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Array
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Array
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