Search

James J. Seidleck

Supervisory Patent Examiner (ID: 17261, Phone: (571)272-1078 , Office: P/1765 )

Most Active Art Unit
1508
Art Unit(s)
1506, 1508, 1512, 1796, 1502, 2401, 1765, 1711, 1507
Total Applications
858
Issued Applications
628
Pending Applications
34
Abandoned Applications
197

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7548055 [patent_doc_number] => 08056036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Semiconductor integrated circuit and method of designing thereof based on TPI' [patent_app_type] => utility [patent_app_number] => 12/153596 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6217 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056036.pdf [firstpage_image] =>[orig_patent_app_number] => 12153596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153596
Semiconductor integrated circuit and method of designing thereof based on TPI May 20, 2008 Issued
Array ( [id] => 5574205 [patent_doc_number] => 20090141566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY' [patent_app_type] => utility [patent_app_number] => 12/110456 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5125 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20090141566.pdf [firstpage_image] =>[orig_patent_app_number] => 12110456 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110456
Structure for implementing memory array device with built in computation capability Apr 27, 2008 Issued
Array ( [id] => 5535433 [patent_doc_number] => 20090235221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'ROUTING CHANNEL DISPLAYING METHOD AND COMPUTER-ACCESSIBLE STORAGE MEDIUM THEREOF' [patent_app_type] => utility [patent_app_number] => 12/108816 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3424 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235221.pdf [firstpage_image] =>[orig_patent_app_number] => 12108816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108816
ROUTING CHANNEL DISPLAYING METHOD AND COMPUTER-ACCESSIBLE STORAGE MEDIUM THEREOF Apr 23, 2008 Abandoned
Array ( [id] => 4678403 [patent_doc_number] => 20080216034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Performance Visualization of Delay in Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/101088 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7072 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216034.pdf [firstpage_image] =>[orig_patent_app_number] => 12101088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/101088
Performance visualization of delay in circuit design Apr 9, 2008 Issued
Array ( [id] => 4511500 [patent_doc_number] => 07949973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Methods of implementing multi-cycle paths in electronic circuits' [patent_app_type] => utility [patent_app_number] => 12/061786 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949973.pdf [firstpage_image] =>[orig_patent_app_number] => 12061786 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061786
Methods of implementing multi-cycle paths in electronic circuits Apr 2, 2008 Issued
Array ( [id] => 4730895 [patent_doc_number] => 20080209367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'RELIABILITY DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/037664 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5826 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209367.pdf [firstpage_image] =>[orig_patent_app_number] => 12037664 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037664
RELIABILITY DESIGN METHOD Feb 25, 2008 Abandoned
Array ( [id] => 5393532 [patent_doc_number] => 20090210845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'COMPUTER PROGRAM PRODUCT, APPARATUS, AND METHOD FOR INSERTING COMPONENTS IN A HIERARCHICAL CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 12/034644 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4551 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210845.pdf [firstpage_image] =>[orig_patent_app_number] => 12034644 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034644
Computer program product, apparatus, and method for inserting components in a hierarchical chip design Feb 19, 2008 Issued
Array ( [id] => 166951 [patent_doc_number] => 07673279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC)' [patent_app_type] => utility [patent_app_number] => 12/033102 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5792 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673279.pdf [firstpage_image] =>[orig_patent_app_number] => 12033102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033102
Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC) Feb 18, 2008 Issued
Array ( [id] => 4869178 [patent_doc_number] => 20080148208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Method for improving a printed circuit board development cycle' [patent_app_type] => utility [patent_app_number] => 12/009938 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148208.pdf [firstpage_image] =>[orig_patent_app_number] => 12009938 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/009938
Method for improving a printed circuit board development cycle Jan 21, 2008 Abandoned
Array ( [id] => 4487570 [patent_doc_number] => 07870527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Method for stacked pattern design of printed circuit board and system thereof' [patent_app_type] => utility [patent_app_number] => 11/970744 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4069 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870527.pdf [firstpage_image] =>[orig_patent_app_number] => 11970744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970744
Method for stacked pattern design of printed circuit board and system thereof Jan 7, 2008 Issued
Array ( [id] => 5411960 [patent_doc_number] => 20090125859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Methods for Optimal Timing-Driven Cloning Under Linear Delay Model' [patent_app_type] => utility [patent_app_number] => 11/938824 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3979 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125859.pdf [firstpage_image] =>[orig_patent_app_number] => 11938824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/938824
Optimal timing-driven cloning under linear delay model Nov 12, 2007 Issued
Array ( [id] => 5411953 [patent_doc_number] => 20090125852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION' [patent_app_type] => utility [patent_app_number] => 11/937644 [patent_app_country] => US [patent_app_date] => 2007-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125852.pdf [firstpage_image] =>[orig_patent_app_number] => 11937644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/937644
METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION Nov 8, 2007 Abandoned
Array ( [id] => 5266940 [patent_doc_number] => 20090119625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => ' Structure for System Architectures for and Methods of Scheduling On-Chip and Across-Chip Noise Events in an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/934804 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7476 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119625.pdf [firstpage_image] =>[orig_patent_app_number] => 11934804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934804
Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit Nov 4, 2007 Issued
Array ( [id] => 5332881 [patent_doc_number] => 20090113358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'MECHANISM FOR DETECTION AND COMPENSATION OF NBTI INDUCED THRESHOLD DEGRADATION' [patent_app_type] => utility [patent_app_number] => 11/931144 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113358.pdf [firstpage_image] =>[orig_patent_app_number] => 11931144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/931144
Mechanism for detection and compensation of NBTI induced threshold degradation Oct 30, 2007 Issued
Array ( [id] => 4616659 [patent_doc_number] => 07992112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Hardware verification programming description generation apparatus, high-level synthesis apparatus, hardware verification programming description generation method, hardware verification program generation method, control program and computer-readable recording medium' [patent_app_type] => utility [patent_app_number] => 11/929304 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12379 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/992/07992112.pdf [firstpage_image] =>[orig_patent_app_number] => 11929304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/929304
Hardware verification programming description generation apparatus, high-level synthesis apparatus, hardware verification programming description generation method, hardware verification program generation method, control program and computer-readable recording medium Oct 29, 2007 Issued
Array ( [id] => 5286724 [patent_doc_number] => 20090100399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS' [patent_app_type] => utility [patent_app_number] => 11/872924 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3655 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20090100399.pdf [firstpage_image] =>[orig_patent_app_number] => 11872924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872924
Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks Oct 15, 2007 Issued
Array ( [id] => 4747491 [patent_doc_number] => 20080092093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Register Transfer Level (RTL) Test Point Insertion Method to Reduce Delay Test Volume' [patent_app_type] => utility [patent_app_number] => 11/858216 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3892 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092093.pdf [firstpage_image] =>[orig_patent_app_number] => 11858216 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858216
Register Transfer Level (RTL) Test Point Insertion Method to Reduce Delay Test Volume Sep 19, 2007 Abandoned
Array ( [id] => 4922099 [patent_doc_number] => 20080070414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'METHOD FOR DESIGNING MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE EMPLOYING THEREOF' [patent_app_type] => utility [patent_app_number] => 11/856746 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7449 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070414.pdf [firstpage_image] =>[orig_patent_app_number] => 11856746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856746
METHOD FOR DESIGNING MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE EMPLOYING THEREOF Sep 17, 2007 Abandoned
Array ( [id] => 5454683 [patent_doc_number] => 20090070720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'System to Identify Timing Differences from Logic Block Changes and Associated Methods' [patent_app_type] => utility [patent_app_number] => 11/853276 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070720.pdf [firstpage_image] =>[orig_patent_app_number] => 11853276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853276
System to Identify Timing Differences from Logic Block Changes and Associated Methods Sep 10, 2007 Abandoned
Array ( [id] => 4706511 [patent_doc_number] => 20080066035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Method and design system of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/896984 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6671 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20080066035.pdf [firstpage_image] =>[orig_patent_app_number] => 11896984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896984
Method and design system of semiconductor integrated circuit Sep 6, 2007 Abandoned
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