Search

James J. Seidleck

Supervisory Patent Examiner (ID: 17261, Phone: (571)272-1078 , Office: P/1765 )

Most Active Art Unit
1508
Art Unit(s)
1506, 1508, 1512, 1796, 1502, 2401, 1765, 1711, 1507
Total Applications
858
Issued Applications
628
Pending Applications
34
Abandoned Applications
197

Applications

Application numberTitle of the applicationFiling DateStatus
11/378665 Performance visualization of delay in circuit design Mar 16, 2006 Abandoned
Array ( [id] => 4979216 [patent_doc_number] => 20070220451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method for modeling and documenting a network' [patent_app_type] => utility [patent_app_number] => 11/378441 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11919 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220451.pdf [firstpage_image] =>[orig_patent_app_number] => 11378441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378441
Method for modeling and documenting a network Mar 15, 2006 Abandoned
Array ( [id] => 4979225 [patent_doc_number] => 20070220460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method for verifying line information in a layout and system thereof' [patent_app_type] => utility [patent_app_number] => 11/374964 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2092 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220460.pdf [firstpage_image] =>[orig_patent_app_number] => 11374964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/374964
Method for verifying line information in a layout and system thereof Mar 14, 2006 Abandoned
Array ( [id] => 4979226 [patent_doc_number] => 20070220461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method and system for sequential equivalence checking with multiple initial states' [patent_app_type] => utility [patent_app_number] => 11/375476 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220461.pdf [firstpage_image] =>[orig_patent_app_number] => 11375476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/375476
Method and system for sequential equivalence checking with multiple initial states Mar 13, 2006 Abandoned
Array ( [id] => 5696117 [patent_doc_number] => 20060156264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Method and apparatus for supporting verification of system, and computer product' [patent_app_type] => utility [patent_app_number] => 11/372393 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 10255 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156264.pdf [firstpage_image] =>[orig_patent_app_number] => 11372393 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/372393
Method and apparatus for supporting verification of system, and computer product Mar 9, 2006 Abandoned
Array ( [id] => 5260805 [patent_doc_number] => 20070214438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'METHOD FOR STATIC POWER CHARACTERIZATION OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/308154 [patent_app_country] => US [patent_app_date] => 2006-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1629 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214438.pdf [firstpage_image] =>[orig_patent_app_number] => 11308154 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308154
METHOD FOR STATIC POWER CHARACTERIZATION OF AN INTEGRATED CIRCUIT Mar 8, 2006 Abandoned
Array ( [id] => 597157 [patent_doc_number] => 07454721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method, apparatus and computer program product for optimizing an integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 11/276374 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2886 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454721.pdf [firstpage_image] =>[orig_patent_app_number] => 11276374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/276374
Method, apparatus and computer program product for optimizing an integrated circuit layout Feb 26, 2006 Issued
Array ( [id] => 600160 [patent_doc_number] => 07441213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof' [patent_app_type] => utility [patent_app_number] => 11/307894 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 2 [patent_no_of_words] => 4526 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441213.pdf [firstpage_image] =>[orig_patent_app_number] => 11307894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/307894
Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof Feb 26, 2006 Issued
Array ( [id] => 5111380 [patent_doc_number] => 20070195295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Mask pattern data forming method, photomask and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/357034 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4068 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195295.pdf [firstpage_image] =>[orig_patent_app_number] => 11357034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357034
Mask pattern data forming method, photomask and method of manufacturing semiconductor device Feb 20, 2006 Issued
Array ( [id] => 905240 [patent_doc_number] => 07340713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method and apparatus for determining a proximity correction using a visible area model' [patent_app_type] => utility [patent_app_number] => 11/357304 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5457 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340713.pdf [firstpage_image] =>[orig_patent_app_number] => 11357304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357304
Method and apparatus for determining a proximity correction using a visible area model Feb 16, 2006 Issued
Array ( [id] => 5679555 [patent_doc_number] => 20060184911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Labeling method and software utilizing the same, and PCB and electronic device utilizing the same' [patent_app_type] => utility [patent_app_number] => 11/352995 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1676 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184911.pdf [firstpage_image] =>[orig_patent_app_number] => 11352995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/352995
Labeling method and software utilizing the same, and PCB and electronic device utilizing the same Feb 13, 2006 Abandoned
Array ( [id] => 5679550 [patent_doc_number] => 20060184906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method and device for designing semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/353073 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7247 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184906.pdf [firstpage_image] =>[orig_patent_app_number] => 11353073 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353073
Method and device for designing semiconductor integrated circuit Feb 13, 2006 Abandoned
Array ( [id] => 5606096 [patent_doc_number] => 20060267612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Automatic design method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/348493 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6777 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267612.pdf [firstpage_image] =>[orig_patent_app_number] => 11348493 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348493
Automatic design method for semiconductor device Feb 6, 2006 Issued
Array ( [id] => 7532692 [patent_doc_number] => 07844926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-30 [patent_title] => 'Specification window violation identification with application in semiconductor device design' [patent_app_type] => utility [patent_app_number] => 11/345554 [patent_app_country] => US [patent_app_date] => 2006-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3672 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844926.pdf [firstpage_image] =>[orig_patent_app_number] => 11345554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/345554
Specification window violation identification with application in semiconductor device design Jan 30, 2006 Issued
Array ( [id] => 5706760 [patent_doc_number] => 20060195808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method for correcting the optical proximity effect' [patent_app_type] => utility [patent_app_number] => 11/336092 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195808.pdf [firstpage_image] =>[orig_patent_app_number] => 11336092 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336092
Method for correcting the optical proximity effect Jan 19, 2006 Abandoned
Array ( [id] => 5621360 [patent_doc_number] => 20060190895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method and program for designing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/334354 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190895.pdf [firstpage_image] =>[orig_patent_app_number] => 11334354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/334354
Method and program for designing semiconductor device Jan 18, 2006 Abandoned
Array ( [id] => 147014 [patent_doc_number] => 07694260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Semiconductor integrated circuit, layout method, layout apparatus and layout program' [patent_app_type] => utility [patent_app_number] => 11/328075 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 8640 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694260.pdf [firstpage_image] =>[orig_patent_app_number] => 11328075 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/328075
Semiconductor integrated circuit, layout method, layout apparatus and layout program Jan 9, 2006 Issued
Array ( [id] => 5679551 [patent_doc_number] => 20060184907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Extracting/reflecting method and hierarchical circuit information with physical information and circuit designing method using the same' [patent_app_type] => utility [patent_app_number] => 11/315594 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 12067 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184907.pdf [firstpage_image] =>[orig_patent_app_number] => 11315594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315594
Extracting/reflecting method and hierarchical circuit information with physical information and circuit designing method using the same Dec 22, 2005 Abandoned
Array ( [id] => 7598011 [patent_doc_number] => 07584442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Method and apparatus for generating memory models and timing database' [patent_app_type] => utility [patent_app_number] => 11/298894 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7392 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584442.pdf [firstpage_image] =>[orig_patent_app_number] => 11298894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/298894
Method and apparatus for generating memory models and timing database Dec 8, 2005 Issued
Array ( [id] => 7495218 [patent_doc_number] => 08032855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Method and apparatus for performing incremental placement on a structured application specific integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/295354 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4374 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032855.pdf [firstpage_image] =>[orig_patent_app_number] => 11295354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295354
Method and apparatus for performing incremental placement on a structured application specific integrated circuit Dec 5, 2005 Issued
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