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James J. Seidleck

Supervisory Patent Examiner (ID: 17261, Phone: (571)272-1078 , Office: P/1765 )

Most Active Art Unit
1508
Art Unit(s)
1506, 1508, 1512, 1796, 1502, 2401, 1765, 1711, 1507
Total Applications
858
Issued Applications
628
Pending Applications
34
Abandoned Applications
197

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5917038 [patent_doc_number] => 20060129955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Printed circuit board development cycle using probe location automation and bead probe technology' [patent_app_type] => utility [patent_app_number] => 11/009117 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6926 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129955.pdf [firstpage_image] =>[orig_patent_app_number] => 11009117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009117
Printed circuit board development cycle using probe location automation and bead probe technology Dec 9, 2004 Abandoned
Array ( [id] => 97147 [patent_doc_number] => 07735048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-08 [patent_title] => 'Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow' [patent_app_type] => utility [patent_app_number] => 10/997639 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10186 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/735/07735048.pdf [firstpage_image] =>[orig_patent_app_number] => 10997639 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997639
Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow Nov 23, 2004 Issued
Array ( [id] => 7248290 [patent_doc_number] => 20050141764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Pattern analysis method and pattern analysis apparatus' [patent_app_type] => utility [patent_app_number] => 10/995356 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 22572 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141764.pdf [firstpage_image] =>[orig_patent_app_number] => 10995356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995356
Pattern analysis method and pattern analysis apparatus Nov 23, 2004 Abandoned
Array ( [id] => 7054251 [patent_doc_number] => 20050275423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'System and method for checking a layout of circuit traces on a PCB' [patent_app_type] => utility [patent_app_number] => 10/997402 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4889 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275423.pdf [firstpage_image] =>[orig_patent_app_number] => 10997402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997402
System and method for checking a layout of circuit traces on a PCB Nov 22, 2004 Abandoned
Array ( [id] => 5749224 [patent_doc_number] => 20060112158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism' [patent_app_type] => utility [patent_app_number] => 10/994114 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4776 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20060112158.pdf [firstpage_image] =>[orig_patent_app_number] => 10994114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994114
Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism Nov 18, 2004 Issued
Array ( [id] => 5734768 [patent_doc_number] => 20060259885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'System and method for analyzing a circuit' [patent_app_type] => utility [patent_app_number] => 11/374283 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3523 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259885.pdf [firstpage_image] =>[orig_patent_app_number] => 11374283 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/374283
System and method for analyzing a circuit Aug 8, 2004 Abandoned
Array ( [id] => 7013828 [patent_doc_number] => 20050066299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method for arranging circuit elements in semiconductor components' [patent_app_type] => utility [patent_app_number] => 10/845763 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066299.pdf [firstpage_image] =>[orig_patent_app_number] => 10845763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845763
Method for arranging circuit elements in semiconductor components May 13, 2004 Abandoned
Array ( [id] => 5122001 [patent_doc_number] => 20070143716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Circuit layout compaction using reshaping' [patent_app_type] => utility [patent_app_number] => 10/596944 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5836 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143716.pdf [firstpage_image] =>[orig_patent_app_number] => 10596944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/596944
Circuit layout compaction using reshaping Dec 28, 2003 Abandoned
Array ( [id] => 5795177 [patent_doc_number] => 20060015858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'System development method and data processing system' [patent_app_type] => utility [patent_app_number] => 10/533062 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 77 [patent_no_of_words] => 13466 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015858.pdf [firstpage_image] =>[orig_patent_app_number] => 10533062 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/533062
System development method and data processing system Oct 6, 2003 Abandoned
Array ( [id] => 366802 [patent_doc_number] => 07484193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method and software for predicting the timing delay of a circuit path using two different timing models' [patent_app_type] => utility [patent_app_number] => 10/651113 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4450 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484193.pdf [firstpage_image] =>[orig_patent_app_number] => 10651113 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651113
Method and software for predicting the timing delay of a circuit path using two different timing models Aug 27, 2003 Issued
Array ( [id] => 6806236 [patent_doc_number] => 20030233630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Methods and systems for process control of corner feature embellishment' [patent_app_type] => new [patent_app_number] => 10/410874 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9912 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20030233630.pdf [firstpage_image] =>[orig_patent_app_number] => 10410874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410874
Methods and systems for process control of corner feature embellishment Apr 9, 2003 Abandoned
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