
James J. Seidleck
Supervisory Patent Examiner (ID: 17261, Phone: (571)272-1078 , Office: P/1765 )
| Most Active Art Unit | |
| Art Unit(s) | |
| Total Applications | |
| Issued Applications | |
| Pending Applications | |
| Abandoned Applications |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 11/009117 | Printed circuit board development cycle using probe location automation and bead probe technology | Dec 9, 2004 | Abandoned |
| 10/997639 | Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow | Nov 23, 2004 | Issued |
| 10/995356 | Pattern analysis method and pattern analysis apparatus | Nov 23, 2004 | Abandoned |
| 10/997402 | System and method for checking a layout of circuit traces on a PCB | Nov 22, 2004 | Abandoned |
| 10/994114 | Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism | Nov 18, 2004 | Issued |
| 11/374283 | System and method for analyzing a circuit | Aug 8, 2004 | Abandoned |
| 10/845763 | Method for arranging circuit elements in semiconductor components | May 13, 2004 | Abandoned |
| 10/596944 | Circuit layout compaction using reshaping | Dec 28, 2003 | Abandoned |
| 10/533062 | System development method and data processing system | Oct 6, 2003 | Abandoned |
| 10/651113 | Method and software for predicting the timing delay of a circuit path using two different timing models | Aug 27, 2003 | Issued |
| 10/410874 | Methods and systems for process control of corner feature embellishment | Apr 9, 2003 | Abandoned |