James M. Mitchell

Array ( [id] => 5780118 [patent_doc_number] => 20060202213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'DEVICE MOUNTING SUBSTRATE AND IMAGE DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/420291 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10223 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20060202213.pdf [firstpage_image] =>[orig_patent_app_number] => 11420291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5683117 [patent_doc_number] => 20060199387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'LOCAL MULTILAYERED METALLIZATION' [patent_app_type] => utility [patent_app_number] => 11/420101 [patent_app_country] => US [patent_app_date] => 2006-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3594 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199387.pdf [firstpage_image] =>[orig_patent_app_number] => 11420101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5730359 [patent_doc_number] => 20060255473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Flip chip interconnect solder mask' [patent_app_type] => utility [patent_app_number] => 11/435555 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5679 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255473.pdf [firstpage_image] =>[orig_patent_app_number] => 11435555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5730276 [patent_doc_number] => 20060255390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/433465 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6054 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255390.pdf [firstpage_image] =>[orig_patent_app_number] => 11433465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5661653 [patent_doc_number] => 20060252249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Solder ball pad surface finish structure of circuit board and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/429766 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4469 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20060252249.pdf [firstpage_image] =>[orig_patent_app_number] => 11429766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 185700 [patent_doc_number] => 07649239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Dielectric spacers for metal interconnects and method to form the same' [patent_app_type] => utility [patent_app_number] => 11/429165 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4803 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649239.pdf [firstpage_image] =>[orig_patent_app_number] => 11429165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5683033 [patent_doc_number] => 20060199303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Carrier for substrate film' [patent_app_type] => utility [patent_app_number] => 11/415766 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199303.pdf [firstpage_image] =>[orig_patent_app_number] => 11415766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5705321 [patent_doc_number] => 20060194369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Carrier for substrate film' [patent_app_type] => utility [patent_app_number] => 11/415550 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20060194369.pdf [firstpage_image] =>[orig_patent_app_number] => 11415550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5680859 [patent_doc_number] => 20060197126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Methods for forming structures including strained-semiconductor-on-insulator devices' [patent_app_type] => utility [patent_app_number] => 11/416423 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15769 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197126.pdf [firstpage_image] =>[orig_patent_app_number] => 11416423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5680858 [patent_doc_number] => 20060197125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Methods for forming double gate strained-semiconductor-on-insulator device structures' [patent_app_type] => utility [patent_app_number] => 11/415784 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15767 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197125.pdf [firstpage_image] =>[orig_patent_app_number] => 11415784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5680856 [patent_doc_number] => 20060197123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Methods for forming strained-semiconductor-on-insulator bipolar device structures' [patent_app_type] => utility [patent_app_number] => 11/415556 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15767 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197123.pdf [firstpage_image] =>[orig_patent_app_number] => 11415556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5680857 [patent_doc_number] => 20060197124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Double gate strained-semiconductor-on-insulator device structures' [patent_app_type] => utility [patent_app_number] => 11/415706 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15764 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197124.pdf [firstpage_image] =>[orig_patent_app_number] => 11415706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5616978 [patent_doc_number] => 20060186510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Strained-semiconductor-on-insulator bipolar device structures' [patent_app_type] => utility [patent_app_number] => 11/412276 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15777 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186510.pdf [firstpage_image] =>[orig_patent_app_number] => 11412276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5680915 [patent_doc_number] => 20060197182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'High frequency integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/411307 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3661 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197182.pdf [firstpage_image] =>[orig_patent_app_number] => 11411307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5733023 [patent_doc_number] => 20060258140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Integrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereof' [patent_app_type] => utility [patent_app_number] => 11/409255 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1203 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258140.pdf [firstpage_image] =>[orig_patent_app_number] => 11409255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5680923 [patent_doc_number] => 20060197190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Method of fabricating wafer-level packaging with sidewall passivation and related apparatus' [patent_app_type] => utility [patent_app_number] => 11/409350 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4464 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197190.pdf [firstpage_image] =>[orig_patent_app_number] => 11409350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5922045 [patent_doc_number] => 20060240361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Method of forming small pitch pattern using double spacers' [patent_app_type] => utility [patent_app_number] => 11/407295 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20060240361.pdf [firstpage_image] =>[orig_patent_app_number] => 11407295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5208236 [patent_doc_number] => 20070246820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Die protection process' [patent_app_type] => utility [patent_app_number] => 11/406666 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2440 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20070246820.pdf [firstpage_image] =>[orig_patent_app_number] => 11406666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10870846 [patent_doc_number] => 08896045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Integrated circuit including sidewall spacer' [patent_app_type] => utility [patent_app_number] => 11/406766 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11406766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5619471 [patent_doc_number] => 20060189005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Methods for fabricating semiconductor devices so as to stabilize the same when contact-bearing surfaces thereof face over test substrates' [patent_app_type] => utility [patent_app_number] => 11/403251 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10142 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20060189005.pdf [firstpage_image] =>[orig_patent_app_number] => 11403251 [rel_patent_id] =>[rel_patent_doc_number] =>)